MAX5825BAUP+ Maxim Integrated, MAX5825BAUP+ Datasheet - Page 7

• Manufacturer Part Number: MAX5825BAUP+
• Description: Digital to Analog Converters - DAC 12-Bit 8Ch V DAC w/I2C Interface
• Manufacturer: Maxim Integrated

Specifications of MAX5825BAUP+

• Rohs: yes
• Number Of Dac Outputs: 8
• Resolution: 12 bit
• Interface Type: I2C
• Settling Time: 4.5 us
• Maximum Operating Temperature: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 1084 mW
• Supply Current: 250 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

ELECTRICAL CHARACTERISTICS (continued)
(V
(Note 3)
Note 3: Electrical specifications are production tested at T
Note 4: DC performance is tested without load, V
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and V
Note 6: Offset and gain calculated from measurements made with V
Note 7: Subject to zero- and full-scale error limits and V
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
Note 10: Guaranteed by design.
Note 11: All channels active at V
Note 12: Unconnected conditions on the ADDR_ inputs are sensed through a resistive pullup and pulldown operation; for proper
Maxim Integrated
Figure 1. I
Output DACs with Internal Reference and I
SDA and SCL Receiving Fall
Time
SDA Transmitting Fall Time
Setup Time for STOP Condition
Bus Capacitance Allowed
Pulse Width of Suppressed Spike
CLR Removal Time Prior to a
Recognized START
CLR Pulse Width Low
LDAC Pulse Width Low
LDAC Fall to SCLK Rise Hold
DD
= 2.7V to 5.5V, V
are guaranteed by design and characterization. Typical specifications are at T
1016 for MAX5824, and code 2 and 254 for MAX5823.
be ignored.
operation, ADDR_ inputs must be connected to V
2
PARAMETER
LDAC
C Serial Interface Timing Diagram
SDA
SCL
CLR
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
t
CLPW
t
F
DDIO
S
= 1.8V to 5.5V, V
t
CLRSTA
FS
t
t
HD;STA
LOW
, unloaded. Static logic inputs with V
SYMBOL
t
t
CLRSTA
SU;STO
t
t
CLPW
LDPW
t
LDH
C
t
t
t
SP
F
F
t
B
F
t
HD;DAT
GND
t
SU;DAT
REF
V
= 0V, C
t
DD
HIGH
= V
= 2.7V to 5.5V
MAX5823/MAX5824/MAX5825
REF
DD
DDIO
A
t
L
F
.
settings.
= +25°C. Specifications over the entire operating temperature range
= 200pF, R
t
SU;STA
, GND, or left unconnected with minimal capacitance.
CONDITIONS
REF
IL
S
r
L
= V
= V
= 2kI, T
DD
GND
t
HD;STA
DD
at code 30 and 4065 for MAX5825, code 8 and
and V
.
A
= -40NC to +125NC, unless otherwise noted.)
IH
A
t
LDH
= +25°C.
= V
t
t
SU;STO
SP
DDIO
C
C
t
20 +
20 +
MIN
LDPW
100
400
0.6
B
B
10
20
20
t
R
/10
/10
for all inputs .
2
P
C Interface
TYP
t
50
BUF
S
MAX
300
250
400
UNITS
pF
ns
ns
Fs
ns
ns
ns
ns
ns
7