MAX5825BAUP+ Maxim Integrated, MAX5825BAUP+ Datasheet - Page 20

• Manufacturer Part Number: MAX5825BAUP+
• Description: Digital to Analog Converters - DAC 12-Bit 8Ch V DAC w/I2C Interface
• Manufacturer: Maxim Integrated

Specifications of MAX5825BAUP+

• Rohs: yes
• Number Of Dac Outputs: 8
• Resolution: 12 bit
• Interface Type: I2C
• Settling Time: 4.5 us
• Maximum Operating Temperature: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 1084 mW
• Supply Current: 250 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Readback of individual RETURN registers is supported
for RETURN commands (B[23:20] = 0111). For this com-
mand, which supports a DAC address, the requested
channel RETURN register content will be returned,
along with the selected DAC address. If all DACs are
selected, readback will begin with RETURN0 content
and will progress through the remaining DAC channels.
The RETURN_ALL (B[23:16] = 11000011) command
behaves identically to the RETURN command with all
DACs selected.
Readback of individual CODE registers is supported for
the CODE commands (B[23:20] = 1000). For this com-
mand, which supports a DAC address, the requested
channel CODE register content will be returned, along
with the selected DAC address. If all DACs are select-
ed, readback will begin with CODE0 content and will
progress through the remaining DAC channels. The
CODE_ALL (B[23:16] = 11000000) command behaves
identically to the CODE command with all DACs selected.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 1001, 1010, 1011). For
these commands, which support a DAC address, the
requested DAC register content will be returned, along
with the selected DAC address. If all DACs are selected,
readback will begin with DAC0 content and will progress
through the remaining DAC channels. The LOAD_ALL
and CODE_ALL_LOAD_ALL commands (B[23:16] =
Table 2. Standard I
Maxim Integrated
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
Output DACs with Internal Reference and I
0
0
0
1
1
1
1
1
1
1
1
All Other Commands (MAX5825)
All Other Commands (MAX5824)
All Other Commands (MAX5823)
COMMAND BYTE (REQUEST)
0
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
DAC SELECTION
DAC SELECTION
DAC SELECTION
DAC SELECTION
DAC SELECTION
X
X
0
0
0
0
X
X
0
0
0
0
2
C User Readback Data
X
X
0
0
1
1
X
X
0
1
0
1
WD
0
READBACk DATA HIGH BYTE
WDOG Timeout Selection[11:4]
0
REF[2:0]
0
RETURNn[11:4]
RETURN0[11:4]
CODEn[11:4]
CODE0[11:4]
DACn[11:4]
DACn[11:4]
DACn[11:4]
DAC0[11:4]
DAC0[11:4]
0
MAX5823/MAX5824/MAX5825
CLR
0
0
11000001 and 11000010, respectively) behave identi-
cally to the LOAD command with all DACs selected.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[7:0], with a
1 indicating the DAC is powered down and a zero indi-
cating the DAC is operational (see
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s current watchdog timer status (WD:0 = nor-
mal, 1 = timed out), reference setting (REF[2:0]), and CLR
condition, along with the device revision (B[10:8] = 001)
and part ID (B[7:0]) in the format as shown in
While the MAX5823/MAX5824/MAX5825 support stan-
dard I
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
REV_ID
(001)
[2:0]
0
2
B8
C readback of selected registers, it is also
0
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
Timeout Selection[3:0] WDM
B7
1
1
1
RETURN0[03:0]
RETURNn[3:0]
CODEn[3:0]
CODE0[3:0]
DACn[3:0]
DACn[3:0]
DACn[3:0]
DAC0[3:0]
DAC0[3:0]
B6
0
0
0
READBACk DATA LOW BYTE
B5
Interface Verification I
0
1
0
Readback Operations
B4
2
0
0
1
C Interface
Table
B3
0
0
0
ADDRESSn[3:0]
ADDRESSn[3:0]
ADDRESSn[3:0]
ADDRESSn[3:0]
ADDRESSn[3:0]
ADDRESS0[3:0]
ADDRESS0[3:0]
ADDRESS0[3:0]
ADDRESS0[3:0]
B2
2).
WL[1:0]
0
0
0
Table
B1
Figure
0
0
0
2.
B0
0
0
0
0
2
20
C
7.