MAX5825BAUP+ Maxim Integrated, MAX5825BAUP+ Datasheet - Page 19

• Manufacturer Part Number: MAX5825BAUP+
• Description: Digital to Analog Converters - DAC 12-Bit 8Ch V DAC w/I2C Interface
• Manufacturer: Maxim Integrated

Specifications of MAX5825BAUP+

• Rohs: yes
• Number Of Dac Outputs: 8
• Resolution: 12 bit
• Interface Type: I2C
• Settling Time: 4.5 us
• Maximum Operating Temperature: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 1084 mW
• Supply Current: 250 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

A master device communicates with the MAX5823/
MAX5824/MAX5825 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in the
Figure 4
of the MAX5823/MAX5824/MAX5825 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4
register writes using a single I
There is no limit as to how many registers the user can
write with a single command. The MAX5823/MAX5824/
MAX5825 support this capability for all user-accessible
write mode commands.
Figure 5. Multiple Register Write Sequence (Standard I
Figure 6. Standard I
Maxim Integrated
Output DACs with Internal Reference and I
SDA
SCL
START
SDA
SCL
and
and
START
0 0 1 A3 A2 A1 A0 W A
Figure
BYTE #1: I
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Figure
WRITE ADDRESS
ADDRESS
2
BYTE #1: I
C Register Read Sequence
0 0 1 A3 A2 A1 A0
2
5. The first byte contains the address
C SLAVE
5), the user can perform multiple
WRITE ADDRESS
2
C SLAVE ADDRESS
A
ACK. GENERATED BY MAX5823/MAX5824/ MAX5825
I
0 0 N
2
2
BYTE #2: COMMAND1
C Write Operations
C command sequence.
WRITE COMMAND1
A
ACK. GENERATED BY MAX5823/MAX5824/MAX5825
W
BYTE
N N N N N
A
23
23
BYTE #2: COMMAND1 BYTE
BYTE #5: COMMANDn BYTE
22
22
WRITE COMMAND1
21
21
(B[23:16])
(B[23:16])
20 19 18 17
20 19 18 17
A
REPEATED
2
START
C Protocol)
MAX5823/MAX5824/MAX5825
0 0 1 A3 A2 A1 A0 R A D D D D D D D D
16
16
BYTE #3: I
READ ADDRESS
A
A
ADDRESS
15 14 13 12 11 10 9
15 14 13 12 11 10 9
BYTE #3: DATA1 HIGH BYTE
BYTE #6: DATAn HIGH BYTE
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in
the address of the MAX5823/MAX5824/MAX5825 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5823/
MAX5824/MAX5825 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are pro-
vided, the MAX5823/MAX5824/MAX5825 will continue to
readback ones.
Readback of the WDOG command (B[23:20] = 0001)
is directly supported, confirming the current watchdog
timeout selection, mask status, and safety level.
2
Combined Format I
C SLAVE
WRITE DATA1
(B[15:8])
(B[15:8])
A
ACK. GENERATED BY I
BYTE #4: DATA1 HIGH
BYTE (B[15:8])
READ DATA
8
8
A
A
BYTE #4: DATA1 LOW BYTE
7 6 5 4 3 2 1
7 6 5 4 3 2 1
BYTE #7: DATAn LOW BYTE
WRITE DATA1
2
C MASTER
Figure
2
(B[7:0])
(B[7:0])
C Readback Operations
A
D D D D D D D D ~A
2
BYTE #5: DATA1 LOW
6. The first byte contains
BYTE (B[15:8])
C Interface
READ DATA
0
0
A
A
COMMAND1
EXECUTED
COMMANDn
EXECUTED
STOP
STOP
19