MAX5825BAUP+ Maxim Integrated, MAX5825BAUP+ Datasheet - Page 17

• Manufacturer Part Number: MAX5825BAUP+
• Description: Digital to Analog Converters - DAC 12-Bit 8Ch V DAC w/I2C Interface
• Manufacturer: Maxim Integrated

Specifications of MAX5825BAUP+

• Rohs: yes
• Number Of Dac Outputs: 8
• Resolution: 12 bit
• Interface Type: I2C
• Settling Time: 4.5 us
• Maximum Operating Temperature: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 1084 mW
• Supply Current: 250 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

The MAX5823/MAX5824/MAX5825 feature a separate
supply input (V
5.5V). Connect V
cessor.
The MAX5823/MAX5824/MAX5825 feature an I
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5823/
MAX5824/MAX5825 and the master at clock rates up
to 400kHz.
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5823/MAX5824/MAX5825 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5823/
MAX5824/MAX5825 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5823/MAX5824/MAX5825 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5823/
MAX5824/MAX5825 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5823/
MAX5824/MAX5825 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
signals. The MAX5823/MAX5824/MAX5825 can accom-
modate bus voltages higher than V
of 5.5V; bus voltages lower than V
mended and may result in significantly increased inter-
face currents. The MAX5823/MAX5824/MAX5825 digital
inputs are double buffered. Depending on the command
SMBus is a trademark of Intel Corp.
Maxim Integrated
Output DACs with Internal Reference and I
Figure 1
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
DDIO
Interface Power Supply (V
DDIO
) for the digital interface (1.8V to
shows the 2-wire interface timing
to the I/O supply of the host pro-
I
2
C Serial Interface
DDIO
DDIO
are not recom-
up to a limit
DDIO
MAX5823/MAX5824/MAX5825
2
C-/
)
issued through the serial interface, the CODE register(s)
can be loaded without affecting the DAC register(s)
using the write command. To update the DAC registers,
either drive the LDAC input low to simultaneously update
all DAC outputs, or use the software LOAD command.
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high
from the master signals the beginning of a transmission
to the MAX5823/MAX5824/MAX5825. The master termi-
nates transmission and frees the bus, by issuing a STOP
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
The MAX5823/MAX5824/MAX5825 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse
as a START condition. Transmissions ending in an
early STOP condition will not impact the internal device
settings. If the STOP occurs during a readback byte,
the transmission is terminated and a later read mode
request will begin transfer of the requested register data
from the beginning (this applies to combined format I
read mode transfers only), interface verification mode
transfers will be corrupted. See
Table 1. I
ADDR1
V
V
V
GND
GND
GND
N.C.
N.C.
N.C.
DDIO
DDIO
DDIO
2
ADDR0
C Slave Address LSBs
V
V
GND
GND
GND
N.C.
N.C.
N.C.
V
DDIO
DDIO
I
DD
2
C START and STOP Conditions
Repeated START Conditions
A3
1
1
1
1
1
1
0
0
0
(Figure
2
I
C Interface
Figure
2
A2
C Early STOP and
2). A START condition
1
1
1
0
0
0
0
0
0
2.
A1
1
1
0
1
1
0
1
1
0
A0
1
0
0
1
0
0
1
0
0
2
17
C