MAX5825BAUP+ Maxim Integrated, MAX5825BAUP+ Datasheet - Page 26

• Manufacturer Part Number: MAX5825BAUP+
• Description: Digital to Analog Converters - DAC 12-Bit 8Ch V DAC w/I2C Interface
• Manufacturer: Maxim Integrated

Specifications of MAX5825BAUP+

• Rohs: yes
• Number Of Dac Outputs: 8
• Resolution: 12 bit
• Interface Type: I2C
• Settling Time: 4.5 us
• Maximum Operating Temperature: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 1084 mW
• Supply Current: 250 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

The WDOG command (B[23:20] = 0001) updates the
watchdog timeout settings and safety levels for the
device. Timeout thresholds are selected in 1ms incre-
ments (1ms to 4095ms are available). The WD_MASK bit
can be used to mask the IRQ operation in response to the
watchdog status, if WD_MASK = 1, watchdog alarms will
not assert IRQ. The watchdog alarm status (WD bit) can
be polled using the available I
mands regardless of WD_MASK settings. A write to this
register will not reset a previously triggered watchdog
alarm (use the WD_RESET command for this purpose).
The watchdog timer refresh and timeout behavior is
defined by the programmable safety level below.
Available safety levels (WL[1:0]):
Low (00): Watchdog timer will refresh with the execution
of any valid user mode command or no-op. Any success-
ful slave address acknowledge qualifies to restart the
watchdog timer (run to the ninth SCL edge), regardless
of the command which follows. Issuing hardware CLR or
LDAC falling edge will also refresh the watchdog timer.
A triggered watchdog alarm does not prevent writes to
*Unless otherwise affected by Watchdog HOLD or CLR configurations as set by the CONFIG command. See the CONFIG register
definition for details.
Maxim Integrated
Table 6. WDOG Command Format
Table 7. Watchdog Safety Level Protection
Output DACs with Internal Reference and I
WATCHDOG
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
WDOG Command
0
10 (High)
01 (Med)
SAFETY
00 (Low)
11 (Max)
LEVEL
0
0
Default Value →
Command Byte
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
ANY COMMAND
REFRESHES
1
WDT
—
—
—
X
X
Don’t Care
X
2
X
C status readback com-
REFRESHES
CLR/LDAC
X
WDOG Command
WDT
—
—
—
C11 C10 C9
X
0
0
TIMEOUT SELECTION[11:4]
MAX5823/MAX5824/MAX5825
0
REFRESHES WDT
PLUS WD_RFRS
Data High Byte
SW_RESET
C8
0
X
X
X
X
C7
0
any register. LDAC and CLR inputs still function after a
watchdog timeout event.
Medium (01): A WD_REFRESH command must be execut-
ed in order to refresh the watchdog timer. Other commands
as well as LDAC or CLR activity do not refresh the watch-
dog timer. A triggered watchdog alarm does not prevent
writes to any register. LDAC and CLR inputs still function
after a watchdog timeout event.
High (10): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands as well
as LDAC or CLR activity do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution
of all POWER, REF, CONFIG, DEFAULT, and RETURN
commands. LDAC and CLR inputs still function after a
watchdog timeout event.
Max (11): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands, as well
as LDAC or CLR activity, do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution of
all POWER, REF, CONFIG, DEFAULT, and RETURN com-
mands. LDAC and CLR are gated and do not function
after a watchdog timeout event.
C6
0
C5
0
ACCESSIBLE AFTER
ALL REGISTERS
WDT TIMEOUT*
B8
C4
0
B7
C3
—
—
0
X
X
SELECTION[3:0]
TIMEOUT
B6
C2
0
B5
C1
0
2
Data Low Byte
C Interface
B4
C0 WDM WL1 WL0
AFTER WDT TIMEOUT*
0
CLR/LDAC AFFECT
DAC REGISTERS
B3
0
B2
—
11: Max
00: Low
X
X
X
WDOG
0
Safety
Level:
High
Med
01:
10:
B1
0
B0
X
X
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