MK10DN64VLF5 Freescale Semiconductor, MK10DN64VLF5 Datasheet - Page 50

• Manufacturer Part Number: MK10DN64VLF5
• Description: ARM Microcontrollers - MCU Kinetis 64K
• Manufacturer: Freescale Semiconductor

Specifications of MK10DN64VLF5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K10P32M50SF0
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
6.8.5.2 VLPR, VLPW, and VLPS mode performance over the full operating
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
50
S11
S12
S13
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S15
S16
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S18
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I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Num.
voltage range
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid
S15
S15
Figure 20. I2S/SAI timing — slave modes
S12
Characteristic
Table 35. I2S/SAI slave mode timing
S19
S13
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
S17
S11
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S12
S16
1
1.71
80
45%
10
2
—
0
10
2
—
S15
Min.
3.6
—
55%
—
—
29
—
—
—
21
Max.
Freescale Semiconductor, Inc.
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
S14
Unit
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S16