ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 95

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

12.11 About the instruction descriptions
12.11.1
12.11.2
12.11.3
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
Operands
Restrictions when using PC or SP
Flexible second operand
Table 12-15. CMSIS intrinsic functions to access the special registers (Continued)
The following sections give more information about using the instructions:
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible in that they can either be a register or a constant. See
“Flexible second operand”
Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack
Pointer (SP) for the operands or destination register. See instruction descriptions for more
information.
Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be
1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3
processor only supports Thumb instructions.
Many general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
Special register
MSP
PSP
•
•
•
•
•
•
•
•
•
•
“Operands” on page 95
“Restrictions when using PC or SP” on page 95
“Flexible second operand” on page 95
“Shift Operations” on page 97
“Address alignment” on page 99
“PC-relative expressions” on page 99
“Conditional execution” on page 100
“Instruction width selection” on page
“Constant”
“Register with optional shift” on page 96
Access
Read
Write
Read
Write
.
CMSIS function
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
102.
SAM3X/A
SAM3X/A
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