ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 1369

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

45.5.2
45.5.3
45.6
45.6.1
45.6.2
45.6.3
45.6.4
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
Functional Description
Interrupt Sources
Conversion Performances
Digital-to-Analog Conversion
Conversion Results
Conversion Triggers
Conversion FIFO
The DACC interrupt line is connected on one of the internal sources of the interrupt controller.
Using the DACC interrupt requires the interrupt controller to be programmed first.
Table 45-2.
For performance and electrical characteristics of the DACC, see the product DC Characteristics
section.
The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is
named DACC Clock. Once a conversion starts the DACC takes 25 clock periods to provide the
analog result on the selected analog output.
When a conversion is completed, the resulting analog value is available at the selected DACC
channel output and the EOC bit in the
Reading the DACC_ISR register clears the EOC bit.
In free running mode, conversion starts as soon as at least one channel is enabled and data is
written in the
data is available at the corresponding analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.
Warning: Disabling the external trigger mode automatically sets the DACC in free running
mode.
A 4 half-word FIFO is used to handle the data to be converted.
As long as the TXRDY flag in the
ready to accept conversion requests by writing data into
which cannot be converted immediately are stored in the DACC FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag
is inactive.
The WORD field of the
word transfer for writing into the FIFO.
In half-word transfer mode only the 16 LSB of DACC_CDR data are taken into account,
DACC_CDR[15:0] is stored into the FIFO.
DACC_CDR[11:0] field is used as data and the DACC_CDR[15:12] bits are used for channel
selection if the TAG field is set in DACC_MR register.
Instance
DACC
DACC Conversion Data
Peripheral IDs
DACC Mode Register
38
ID
DACC Interrupt Status Register
Register, then 25 DACC Clock periods later, the converted
DACC Interrupt Status
allows the user to switch between half-word and
DACC Conversion Data
Register, is set.
is active the DAC Controller is
SAM3X/A
SAM3X/A
Register. Data
1369
1369