ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 202

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

12.23.2
• PRIVDEFENA
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any
enabled region causes a fault.
1: If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.
When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority
over this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit
1: the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
• ENABLE
Enables the MPU:
0: MPU disabled
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
For privileged accesses, the default memory map is as described in
software that does not address an enabled memory region behaves as defined by the default memory map.
202
202
31
23
15
7
SAM3X/A
SAM3X/A
MPU Control Register
30
22
14
6
The MPU CTRL register:
See the register summary in
assignments are:
• enables the MPU
• enables the default memory map background region
• enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
Reserved
29
21
13
5
28
20
12
4
Table 12-35 on page 200
Reserved
Reserved
Reserved
27
19
11
“Memory model” on page
3
PRIVDEFENA
26
18
10
2
for the MPU CTRL attributes. The bit
71. Any access by privileged
HFNMIENA
25
17
9
1
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
ENABLE
24
16
8
0