ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 107

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

12.12.3.2
12.12.3.3
12.12.3.4
12.12.3.5
12.12.4
12.12.4.1
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
STR
LDRSB
STR
LDR and STR, unprivileged
Operation
Restrictions
Condition flags
Examples
Syntax
R0, [R5, R1]
R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is
specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
In these instructions:
When Rt is PC in a word load instruction:
These instructions do not change the flags.
Load and Store with unprivileged access.
where:
op
type is one of:
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
• if the instruction is conditional, it must be the last instruction in the IT block.
halfword-aligned address
op{type}T{cond} Rt, [Rn {, #offset}]
LDR
STR
B
SB
H
is one of:
Load Register.
Store Register.
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
; Store value of R0 into an address equal to
; sum of R5 and R1
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
; and four times R2
“Address alignment” on page
; immediate offset
99.
SAM3X/A
SAM3X/A
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