ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 369
ATSAM3X4EA-AU
Manufacturer Part Number
ATSAM3X4EA-AU
Description
ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
Manufacturer
Atmel
Datasheet
1.ATSAM3X8EA-AU.pdf
(1467 pages)
Specifications of ATSAM3X4EA-AU
Rohs
yes
Core
ARM Cortex M3
Processor Series
SAM3X
Data Bus Width
32 bit
Maximum Clock Frequency
84 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 3.6 V
Operating Temperature Range
- 40 C to +85 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
60
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11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
• When the destination peripheral has been defined as the flow controller, if the destination
• When a Memory to Peripheral transfer occurs, if the destination peripheral has been defined
• You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte,
• After the software disables a channel by writing into the channel disable register, it must re-
• If you program the BTSIZE field in the DMAC_CTRLA as zero, and the DMAC has been
• When hardware handshaking interface protocol is fully implemented, a peripheral is expected
• Multiple Transfers involving the same peripheral must not be programmed and enabled on
• When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must
width is smaller than the source width, then a data loss may occur, and the loss is equal to
the Source Single Transfer size in bytes- destination Single Transfer size in bytes.
as the flow controller, then a prefetch operation is performed. It means that data is extracted
from the memory before any request from the peripheral is generated.
half-word and word aligned address depending on the source width and destination width.
enable the channel only after it has polled a 0 in the corresponding channel enable status
register. This is because the current AHB Burst must terminate properly.
defined as the flow controller, then the channel is automatically disabled.
to deassert any sreq or breq signals on receiving the ack signal irrespective of the request
the ack was asserted in response to.
different channels, unless this peripheral integrates several hardware handshaking
interfaces.
be enabled before the Peripheral. If you do not ensure this and the First DMAC request is
also the last transfer, the DMAC Channel might miss a Last Transfer Flag.
SAM3X/A
SAM3X/A
369
369
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