ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 444

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

27.10.3
27.10.3.1
27.10.3.2
444
444
SAM3X/A
SAM3X/A
Write Waveforms
NWE Waveforms
NCS Waveforms
The write protocol is similar to the read protocol. It is depicted in
starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same as those applied in read opera-
tions, but are separately defined:
Figure 27-10. Write Cycle
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NBS0, NBS1,
A0, A1
the NWE falling edge.
rising edge.
the NWE rising edge.
the NCS falling edge.
NCS rising edge.
NCS rising edge.
A [23:2]
NWE
MCK
NCS
NCS_WR_SETUP
NWE_SETUP
NCS_WR_PULSE
NWE_PULSE
NWE_CYCLE
NWE_HOLD
Figure
NCS_WR_HOLD
27-10. The write cycle
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12