SSTV16859MTDX Fairchild Semiconductor, SSTV16859MTDX Datasheet - Page 5

• Manufacturer Part Number: SSTV16859MTDX
• Description: IC REG 13BIT DUAL SSTL-2 64TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74SSTVr

Specifications of SSTV16859MTDX

• Logic Type: Register with SSTL-2 Compatible I/O and Reset
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 13
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Package Type: TSSOP W
• Propagation Delay Time: 5ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Output Type: Standard
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200(Min)MHz
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R
R
R
f
t
t
(Note 7)
t
(Note 7)
t
t
t
t
t
C
MAX
W
ACT
INACT
S
H
REM
PHL
PHL
DC Electrical Characteristics
AC Electrical Characteristics
Note 6: Refer to Figure 1 through Figure 7.
Note 7: This parameter is not production tested.
Note 8: For data signal input slew rate
Note 9: For data signal input slew rate
Note 10: For CK, CK signals input slew rates are
Capacitance
Note 11: T
OH
OL
O
Symbol
IN
Symbol
Symbol
, t
PLH
A
Output HIGH On Resistance
Output LOW On Resistance
| R
Maximum Clock Frequency
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
data and clock inputs must be held at valid levels
(not floating) after RESET LOW
Setup Time, Fast Slew Rate (Note 8)(Note 9) (Figure 5)
Setup Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5)
Hold Time, Fast Slew Rate (Note 8)(Note 10) (Figure 5)
Hold Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5)
Reset Removal Time (Figure 7)
Propagation Delay CK, CK to Q
Propagation Delay RESET to Q
Data Pin Input Capacitance
CK, CK - Input Capacitance
RESET
25 C, f
OH
- R
OL
1 MHz, Capacitance is characterized but not tested.
|
Parameter
Parameter
(Note 11)
1 V/ns.
0.5 V/ns and
Parameter
n
n
(Figure 4)
(Figure 6)
1 V/ns.
I
I
I
OH
OL
O
1 V/ns.
Min
2.2
2.2
2.3
20 mA, T
20 mA
Conditions
20 mA
(Note 6)
(Continued)
A
Typ
25 C
5
2.3 to 2.7
2.3 to 2.7
Max
3.2
3.2
3.3
V
(V)
2.5
DD
T
V
A
DD
0.75
0.75
Min
200
2.5
0.9
0.9
1.1
22
22
10
Units
0 C to 70 C, C
pF
pF
pF
2.5V
Min
7
7
0.2V; V
V
V
V
DD
DD
DD
Typ
L
2.5V, V
2.5V, V
2.5V, V
DDQ
Typ
30 pF, R
2.5V
I
ICR
I
Conditions
V
V
www.fairchildsemi.com
REF
DD
L
Max
1.25, V
2.8
5.0
0.2V
or GND
Max
50
20
20
4
310 mV
I(PP)
360 mV
Units
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns