S9S12G128F0VLLR Freescale Semiconductor, S9S12G128F0VLLR Datasheet - Page 763
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S9S12G128F0VLLR
Manufacturer Part Number
S9S12G128F0VLLR
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLLR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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23.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000D
PR[2:0]
Reset
TCRE
Field
TOI
7
3
2
W
R
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for
Note: This bit and feature is available only when channel 7 exists. If channel 7 doesn’t exist, this bit is reserved.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in
TOI
0
7
TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.
a more detail explanation please refer to
Writing to reserved bit has no effect. Read from reserved bit return a zero.
= Unimplemented or Reserved
Figure 23-19. Timer System Control Register 2 (TSCR2)
0
0
6
PR2
0
0
0
0
1
1
1
1
Table
MC9S12G Family Reference Manual, Rev.1.23
Table 23-14. TSCR2 Field Descriptions
Table 23-15. Timer Clock Selection
23-15.
0
0
5
PR1
0
0
1
1
0
0
1
1
0
0
4
Section 23.4.3, “Output Compare
Description
PR0
0
1
0
1
0
1
0
1
TCRE
0
3
Bus Clock / 128
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 1
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Timer Clock
PR2
0
2
Timer Module (TIM16B8CV3)
PR1
0
1
PR0
0
0
765
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