S9S12G128F0VLLR Freescale Semiconductor, S9S12G128F0VLLR Datasheet - Page 490
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S9S12G128F0VLLR
Manufacturer Part Number
S9S12G128F0VLLR
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLLR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Analog-to-Digital Converter (ADC10B12CV2)
edge or level sensitive with polarity control.
combinations of control bits and their effect on the external trigger function.
In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register
first and in the following enable the external trigger mode by bit ETRIGE.
In either level or edge sensitive modes, the first conversion begins when the trigger is received.
Once ETRIGE is enabled a conversion must be triggered externally after writing to ATDCTL5 register.
During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error flag
ETORF is set.
If level sensitive mode is active and the external trigger de-asserts and later asserts again during a
conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left
active in level sensitive mode when a sequence is about to complete, another sequence will be triggered
immediately.
13.4.2.2
Each ATD input pin can be switched between analog or digital input functionality. An analog multiplexer
makes each ATD input pin selected as analog input available to the A/D converter.
The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer.
Each pad input signal is buffered to the digital port register.
This buffer can be turned on or off with the ATDDIEN register for each ATD input pin.
This is important so that the buffer does not draw excess current when an ATD input pin is selected as
analog input to the ADC10B12C.
492
General-Purpose Digital Port Operation
ETRIGLE
X
X
0
0
1
1
ETRIGP
X
X
0
1
0
1
Table 13-23. External Trigger Control Bits
MC9S12G Family Reference Manual,
ETRIGE
0
0
1
1
1
1
Table 13-23
SCAN
X
X
X
X
0
1
gives a brief description of the different
Ignores external trigger. Performs one
conversion sequence and stops.
Ignores external trigger. Performs
continuous conversion sequences.
Trigger falling edge sensitive. Performs
one conversion sequence per trigger.
Trigger rising edge sensitive. Performs one
conversion sequence per trigger.
Trigger low level sensitive. Performs
continuous conversions while trigger level
is active.
Trigger high level sensitive. Performs
continuous conversions while trigger level
is active.
Rev.1.23
Description
Freescale Semiconductor
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