S9S12G128F0VLLR Freescale Semiconductor, S9S12G128F0VLLR Datasheet - Page 383
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S9S12G128F0VLLR
Manufacturer Part Number
S9S12G128F0VLLR
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLLR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.3.2.9
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit (see also
In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the
COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run.
Read: Anytime
Write:
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL0 or COPSOCSEL1 bit (writing a different value) or loosing UPOSC status
while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period.
In Normal Mode the COP time-out period is restarted if either of these conditions is true:
In Special Mode, any write access to CPMUCOP register restarts the COP time-out period.
Freescale Semiconductor
0x003C
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
Reset
1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode
2. WCOP, CR2, CR1, CR0:
1. Writing a non-zero value to CR[2:0] (anytime in Special Mode, once in Normal Mode) with
2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
details.
W
R
— Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect
— Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect.
WRTMASK = 0.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
S12CPMU COP Control Register (CPMUCOP)
F
7
= Unimplemented or Reserved
RSBCK
Figure 10-12. S12CPMU COP Control Register (CPMUCOP)
0
6
MC9S12G Family Reference Manual, Rev.1.23
WRTMASK
0
0
5
Table
0
0
4
10-6).
S12 Clock, Reset and Power Management Unit (S12CPMU)
0
0
3
CR2
F
2
CR1
F
1
CR0
F
0
385
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