S9S12G128F0VLLR Freescale Semiconductor, S9S12G128F0VLLR Datasheet - Page 762
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S9S12G128F0VLLR
Manufacturer Part Number
S9S12G128F0VLLR
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLLR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Module (TIM16B8CV3)
Write: Anytime.
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
23.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
764
Module Base + 0x000C
EDGnB
EDGnA
C7I:C0I
Reset
Field
Field
7:0
7:0
W
R
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
C7I
0
7
C6I
0
6
EDGnB
Figure 23-18. Timer Interrupt Enable Register (TIE)
Table 23-12. Edge Detector Circuit Configuration
0
0
1
1
Table 23-11. TCTL3/TCTL4 Field Descriptions
MC9S12G Family Reference Manual,
Table 23-13. TIE Field Descriptions
C5I
EDGnA
0
5
0
1
0
1
Capture on any edge (rising or falling)
C4I
0
4
Capture on falling edges only
Capture on rising edges only
Description
Description
Capture disabled
Configuration
C3I
0
3
Rev.1.23
C2I
0
2
Freescale Semiconductor
C1I
0
1
C0I
0
0
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