FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 5

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

A watchdog timer can also be used to drive an active
reset signal. The watchdog is a free-running
programmable timer. The timeout period can be
software programmed from 60 ms to 1.8 seconds in
60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
The watchdog also incorporates a window timer
feature that allows a delayed start. The starting time
and ending time defines the window and each may be
set independently.
resolution and 0 ms to 775 ms range.
The watchdog EndTime value is located in register
0Ch, bits 4-0, the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 0Ah. Writing the correct
pattern will also cause the timer to load new timeout
values. Writing other patterns to this address will not
affect its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
VDD
VTP
RST
Watchdog
Timebase
Restart
RST
100 ms
Figure 3. Watchdog Timer
clock
Figure 4. Window Timer
Figure 2. Low V
Start
Time
Timer Settings
Window
Down Counter
The starting time has 25 ms
Watchdog
WR3-0 = 1010b
DD
End
Time
Reset
100 ms (max)
WDE
to restart
t
RPU
/RST
timer as described above. This assures that the full
timeout is provided immediately after enabling. The
watchdog is disabled when V
Note setting the EndTime timeout setting to all
zeroes (00000b) disables the timer to save power.
The listing below summarizes the watchdog bits.
Watchdog StartTime
Watchdog EndTime
Watchdog Enable
Watchdog Restart
Watchdog Flags
The programmed StartTime value is a guaranteed
maximum time while the EndTime value is a
guaranteed minimum time, and both vary with
temperature and V
additional controls associated with its operation. The
nonvolatile enable bit WDE allows the /RST to go
active if the watchdog reaches the timeout without
being restarted. If a reset occurs, the timer will restart
on the rising edge of the reset pulse. If WDE is not
enabled, the watchdog timer still runs but has no
effect on /RST. The second control is a nibble that
restarts the timer, thus preventing a reset. The timer
should be restarted after changing the timeout value.
This procedure must be followed to properly load the
watchdog registers:
The restart command in step 3 must be issued before
t
timer starts counting when the restart command is
issued.
Manual Reset
The /RST is a bi-directional signal allowing the
FM33256B to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms (max.). This effectively filters and de-
bounces a reset switch. After this timeout (t
user may continue pulling down on the /RST pin, but
SPI commands will not be locked out.
DOG2
1.
2.
3.
, which was programmed in step 2. The window
Write the StartTime value
Write the EndTime value and WDE=1 0Ch
Issue a Restart command
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
DD
Ramtron International Corporation
voltage. The watchdog has two
WDST4-0 0Bh, bits 4-0
WDET4-0 0Ch, bits 4-0
WDE
WR3-0
EWDF,
LWDF
(800) 545-FRAM, [phone]
DD
drops below V
0Ch, bit 7
0Ah, bits 3-0
09h, bit 7
09h, bit 6
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Page 5 of 28
Address
0Bh
0Ah
RPU
), the
TP
.