FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 23

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes.
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike SPI-bus
EEPROMs, the FM33256B can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN op-
code with /CS being asserted and deasserted. The
next op-code is a WRITE. The WRITE op-code is
followed by a two-byte address value. This is the
starting address of the first data byte of the write
operation. Subsequent bytes are data bytes, which are
written sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks and keeps /CS low. A write operation will be
terminated when a write-protected address is directly
accessed or when the device has internally
incremented the address into a write-protected space.
If the last address (7FFFh) is reached, the counter
will roll over to 0000h. Data is written MSB first.
The rising edge of /CS terminates a WRITE
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
SCK
SCK
CS
SO
CS
SO
SI
SI
0
0
0
0
0
0
1
1
0
0
2
2
Op-code
Op-code
Hi-Z
Hi-Z
0
0
3
3
0
0
4
4
0
0
5
5
1
1
6
6
0
1
7
7
MSB
MSB
X
X
0
0
(WREN must precede WRITE)
Figure 22. Memory Write
Figure 23. Memory Read
14
14
1
1
13
13
2
2
16-bit Address
16-bit Address
12
12
3
3
11
11
4
4
operation. A write operation is shown in Figure 22.
Note: Although the WREN op-code is not shown in
the timing diagram, it is required prior to sending the
WRITE command.
EEPROMs use page buffers to increase their write
throughput. This compensates for the technology’s
inherently slow write operations. F-RAM memories
do not have page buffers because each byte is written
to the F-RAM array immediately after it is clocked in
(after the 8
to be written without page buffer delays.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following the READ command is
a two-byte address value. This is the starting address
of the first byte of the read operation. After the op-
code and address are issued, the device drives out the
read data on the next 8 clocks.
ignored during read data bytes. Subsequent bytes are
data bytes, which are read out sequentially.
Addresses are incremented internally as long as the
bus master continues to issue clocks and /CS is low.
If the last address is reached (7FFFh), the counter
will roll over to 0000h. Data is read MSB first. The
rising edge of /CS terminates a READ operation. A
read operation is shown in Figure 23.
1
1
6
6
LSB
LSB
0
0
7
7
MSB
MSB
th
7
7
0
0
clock). This allows any number of bytes
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
1
6
1
6
Ramtron International Corporation
2
5
5
2
Data Out
Data In
3
4
3
4
(800) 545-FRAM, [phone]
4
3
4
3
5
2
5
2
www.ramtron.com
The SI input is
1
6
6
1
LSB
LSB
7
0
7
0
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0
0
7
7