FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 16

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
RC
WC
POLL
CP
0Ch
WDE
WDET(4:0) Watchdog EndTime: Sets the ending time for the watchdog window timer with 60 ms (min.) resolution. The
0Bh
WDST(4:0) Watchdog StartTime. Sets the starting time for the watchdog window timer with 25 ms (max.) resolution. The
Read Counter. Setting this bit to 1 takes a snapshot of the two counter bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Write Counter. Setting this bit to a 1 allows the user to write the counter bytes. While WC=1, the counter is
blocked from count events on the CNT pin. The WC bit must be cleared by the user to activate the counter.
Polled Mode: When POLL=1, the CNT pin is sampled for 30µs every 125ms. If POLL is set, the NVC bit is
internally cleared and the CP bit is set to detect a rising edge. The RTC oscillator must be enabled (/OSCEN=0)
to operate in polled mode. When POLL=0, CNT pin is continuously active. Nonvolatile, read/write.
The CNT pin detects falling edges when CP = 0, rising edges when CP = 1. Nonvolatile, read/write.
Watchdog Control
Watchdog Enable: When WDE=1, a watchdog timer fault will cause the /RST signal to go active. When WDE =
0 the timer runs but has no effect on the /RST pin. Nonvolatile, read/write.
window timer allow independent leading and trailing edges (start and end of window) to be set. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). To save power (disable
timer circuit), the EndTime may be set to all zeroes. Nonvolatile, read/write.
Watchdog Control
window timer allow independent leading and trailing edges (start and end of window) to be set. New watchdog
timer settings are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). Nonvolatile,
read/write.
WDE
D7
D7
-
Watchdog EndTime
Disables Timer
Watchdog StartTime
0 ms (default)
157.5 ms
217.5 ms
1200 ms
1260 ms
1320 ms
1740 ms
1800 ms
1860 ms
15.0 ms
22.5 ms
(min.)
(min.)
150 ms
165 ms
120 ms
180 ms
7.5 ms
60 ms
.
.
.
.
.
.
.
.
.
.
.
.
D6
D6
-
-
4000 ms
4200 ms
4400 ms
5800 ms
6000 ms
6200 ms
525 ms
500 ms
725 ms
550 ms
(max.)
400 ms
600 ms
50 ms
200 ms
25 ms
75 ms
(max.)
D5
D5
-
-
.
.
.
.
.
.
.
.
.
.
.
.
WDET4 WDET3 WDET2 WDET1 WDET0
WDST4 WDST3 WDST2 WDST1 WDST0
WDET4
WDST4
D4
D4
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
WDET3
WDST3
D3
D3
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
WDET2
WDST2
Ramtron International Corporation
0
0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
D2
D2
(800) 545-FRAM, [phone]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WDET1
WDST1
D1
D1
www.ramtron.com
Page 16 of 28
WDET0
WDST0
D0
D0