FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 22

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

WRPC – Write Processor Companion
The WRPC command is used to set companion
control settings. A WREN command is required
prior to sending the WRPC command. Following the
WRPC op-code, a single-byte register address is
sent. The controller then drives one or more bytes to
Status Register & Write Protection
The write protection features of the FM33256B are
multi-tiered. To write the memory, a WREN op-code
must first be issued, followed by a WRITE op-code.
A Status Register associated with the memory has a
write enable latch bit (WEL) that is internally set
when WREN is issued.
Writes to certain memory blocks are controlled by
the Block Protect bits in the Status Register. The BP
bits may be changed by using the WRSR command.
The Status Register is organized as follows.
Bits 7, 5, 4, and 0 are fixed at 0, bit 6 is fixed at 1,
and none of these bits can be modified. Note that bit
0 (Ready in EEPROMs) is unnecessary as the F-
RAM writes in real-time and is never busy. The BP1
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
SCK
Bit
Name
SCK
SO
CS
CS
SO
SI
SI
7
0
0
0
0
0
Table 6. Status Register
6
1
0
1
0
1
5
0
0
2
0
2
o p - c o d e
o p - c o d e
1
1
3
3
Hi-Z
Hi-Z
4
0
0
4
0
4
BP1
3
0
5
0
5
1
6
1
6
BP0
Figure 21. Processor Companion Write
Figure 20. Processor Companion Read
2
0
7
1
7
MSB
MSB
7
7
0
0
(WREN must precede WRPC)
WEL
6
1
6
1
1
Register Address
Register Address
5
5
2
2
0
0
4
3
4
3
3
4
3
4
5
2
5
2
program the companion registers. When writing
multiple data bytes, the internal register address will
wrap around to 00h after 1Dh is reached. The rising
edge of /CS terminates a WRPC operation. See
Figure 21.
6
1
and BP0 control software write-protection features.
They are nonvolatile (shaded yellow). The WEL flag
indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the Status
Register has no effect on its state, since this bit is
internally set and cleared via the WREN and WRDI
commands, respectively. BP1 and BP0 are memory
block write protection bits. They specify portions of
memory that are write-protected as shown in the
following table.
6
1
LSB MSB
LSB
BP1
0
7
0
7
0
0
1
1
Table 7. Block Memory Write Protection
MSB
7
0
7
0
6
1
6
1
BP0
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
5
5
2
0
1
0
1
2
4
3
4
Data
3
Data Out
Ramtron International Corporation
3
4
Protected Address Range
None
Upper ¼
Upper ½
All
3
4
5
2
5
2
(800) 545-FRAM, [phone]
6
1
6
1
LSB
LSB
7
0
7
0
www.ramtron.com
LSB
LSB
7
0
7
0
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