LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 385

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LFE2-6E-5TN144CES

Manufacturer Part Number
LFE2-6E-5TN144CES
Description
Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
Manufacturer
Lattice Semiconductor
Datasheet
Lattice Semiconductor
September 2007
February 2008
August 2007
(cont.)
Date
Version
(cont.)
02.8
02.9
03.0
Ordering Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
Architecture
Section
(cont.)
sysCLOCK GPLL timing has been updated.
Added ECP2M50 (484/672/900-fpBGA), ECP2M70 (900-fpBGA) and
ECP2M100 (900-fpBGA) pinout information.
1156-fpBGA package option has been removed from the LatticeECP2M
family.
Added Thermal Management text section.
Added LVCMOS33D description.
LatticeECP2M Supply Current has been updated.
Typical Building Block Function Performance, External Switching
Characteristics, Internal Switching Characteristics, Family Timing
Adders, sysCLOCK GPLL Timing, sysCLOCK SPLL Timing, DLL Tim-
ing and sysCONFIG Port Timing Specificaions have been updated (tim-
ing rev. A 0.11).
Figure 3-9. Read/Write Mode (Normal) and Figure 3-10. Read/Write
Mode with Input and Output Registers have been updated.
Table 3-8. Channel output Jitter (Max) has been updated.
Signal description has been updated.
Added 1152-fpBGA pinouts for the ECP2M70 and ECP2M100.
7-3
LatticeECP2/M Family Data Sheet
Change Summary
Revision History

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