LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 110
LFE2-6E-5TN144CES
Manufacturer Part Number
LFE2-6E-5TN144CES
Description
Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
Manufacturer
Lattice Semiconductor
Datasheet
1.LFE26E5TN144C.pdf
(385 pages)
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Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.)
Available DDR-Interfaces per I/O
Bank
PCI Capable I/Os per Bank
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
1
Pin Type
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
4-10
484 fpBGA
46
46
0
0
2
0
3
3
1
2
0
0
0
0
0
0
0
0
LFE2-50
LatticeECP2/M Family Data Sheet
672 fpBGA
62
68
0
0
3
3
4
4
4
3
0
0
0
0
0
0
0
0
672 fpBGA
Pinout Information
62
68
0
0
3
3
4
4
4
3
0
0
0
0
0
0
0
0
LFE2-70
900 fpBGA
72
80
0
0
4
3
4
5
4
4
0
0
0
0
0
0
0
0
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