LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 114

• Manufacturer Part Number: LFE2-6E-5TN144CES
• Description: Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
• Manufacturer: Lattice Semiconductor

LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100
(Cont.)
Lattice Semiconductor
Available DDR-Interfaces
per I/O Bank
PCI Capable I/Os per Bank
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
1
Pin Type
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA
50
60
52
60
0
0
2
2
3
2
1
3
0
0
0
0
0
0
LFE2M50
4-14
24
60
54
60
0
0
4
3
1
3
3
4
0
0
0
0
0
0
48
50
60
68
0
0
2
1
3
3
2
3
0
0
0
0
0
0
LatticeECP2/M Family Data Sheet
48
40
62
70
0
0
4
3
3
2
3
4
0
0
0
0
0
0
LFE2M70
72
64
40
40
66
74
0
0
4
4
3
3
4
4
0
0
0
0
Pinout Information
48
40
62
70
0
0
4
3
3
2
3
4
0
0
0
0
0
0
LFE2M100
44
46
82
90
80
80
0
0
4
5
3
3
5
5
0
0
0
0