LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 27

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LFE2-6E-5TN144CES

Manufacturer Part Number
LFE2-6E-5TN144CES
Description
Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
Manufacturer
Lattice Semiconductor
Datasheet
Lattice Semiconductor
MULTADDSUB sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-25
shows the MULTADDSUB sysDSP element.
Figure 2-25. MULTADDSUB
Multiplicand A0
Multiplicand A1
Multiplier B0
Multiplier B1
Signed A
Signed B
Addn
Shift Register B Out
Shift Register B In
n
n
Input Data
Register B
Input Data
Register B
n
n
n
n
n
Register
Register
Register
Input
Input
Input
m
m
Input Data
Register A
Input Data
Register A
m
Shift Register A Out
m
m
Shift Register A In
m
m
Pipeline
Register
Register
Register
Pipeline
Pipeline
Pipe
Pipe
Pipe
Reg
Reg
Reg
m
n
m
n
2-24
To Add/Sub
To Add/Sub
To Add/Sub
Multiplier
Multiplier
Register
Pipeline
Register
Pipeline
x
x
(default)
(default)
m+n
m+n
LatticeECP2/M Family Data Sheet
Add/Sub
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
(default)
m+n+1
(default)
m+n+1
Architecture
Output

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