A42MX09-1TQG176M Microsemi, A42MX09-1TQG176M Datasheet - Page 49

• Manufacturer Part Number: A42MX09-1TQG176M
• Description: Ic Fpga Mx Sgl Chip 14k 176-Tqfp
• Manufacturer: Microsemi

Pin Descriptions
CLK/A/B, I/O
Clock inputs for clock distribution networks. CLK is for
40MX while CLKA and CLKB are for 42MX devices. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK, I/O
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Input LOW supply voltage.
I/O
Input, output, tristate, or bidirectional buffer. Input and
output levels are compatible with standard TTL
specifications. Unused I/O pins are configured by the
Designer software as shown in
Table 1-15 • Configuration of Unused I/Os
In all cases, it is recommended to tie all unused I/O pins
to LOW on the board. This applies to all dual-purpose
pins when configured as I/Os as well.
MODE
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). To provide verification capability, the MODE
pin should be held HIGH. To facilitate this, the MODE pin
should be tied to GND through a 10kΩ resistor so that
the MODE pin can be pulled HIGH when required.
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
Device
A40MX02, A40MX04
A42MX09, A42MX16
A42MX24, A42MX36
Global Clock
Diagnostic Clock
Ground
Input/Output
Mode
No Connection
Table
Configuration
1-15.
Pulled LOW
Pulled LOW
Tristated
v3.1
PRA/B, I/O
The Probe pin is used to output data from any user-
defined design node within the device. Each diagnostic
pin can be used in conjunction with the other probe pin
to allow real-time diagnostic output of any signal path
within the device. The Probe pin can be used as a user-
defined I/O when verification has been completed. The
pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. The Probe
pin is accessible when the MODE pin is High. This pin
functions as an I/O when the MODE pin is Low.
QCLKA,B,C,D, I/O Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not
used as a register control signal, these pins can function
as general-purpose I/Os.
SDI, I/O
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
SDO, TDO, I/O
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an
output while the "checksum" is run. It will return to user
I/O when "checksum" is complete.
TCK, I/O
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when
"Reserve JTAG" is not checked in the Designer software.
BST pins are only available in the A42MX24 and
A42MX36 devices.
TDI, I/O
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when "Reserve JTAG" is not checked in the
Designer software. BST pins are only available in the
A42MX24 and A42MX36 devices.
40MX and 42MX Automotive FPGA Families
Serial Data Input
Serial Data Output
Test Clock
Test Data In
Probe
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