A42MX09-1TQG176M Microsemi, A42MX09-1TQG176M Datasheet - Page 48

• Manufacturer Part Number: A42MX09-1TQG176M
• Description: Ic Fpga Mx Sgl Chip 14k 176-Tqfp
• Manufacturer: Microsemi

Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V
1 -4 4
Parameter
t
t
t
t
t
d
d
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
GHL
LSU
LH
LCO
ACO
TLH
THL
40MX and 42MX Automotive FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer tool.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
G-to-Pad LOW
I/O Latch Set-Up
I/O Latch Hold
I/O Latch Clock-to-Out (Pad-to-Pad), 32 I/O
Array Clock-to-Out (Pad-to-Pad), 32 I/O
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
PD1
+ t
RD1
CCA
+ t
= 4.75V, T
Description
PDn
, t
CO
+ t
J
= 125°C (Continued)
RD1
+ t
v3.1
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Min.
0.8
0.0
Std. Speed
Max.
13.0
0.11
0.11
5.0
9.5
Units
ns/pF
ns/pF
ns
ns
ns
ns
ns