A42MX09-1TQG176M Microsemi, A42MX09-1TQG176M Datasheet - Page 12

• Manufacturer Part Number: A42MX09-1TQG176M
• Description: Ic Fpga Mx Sgl Chip 14k 176-Tqfp
• Manufacturer: Microsemi

Design Consideration
It is recommended to use a series 70Ω termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70Ω series termination is used
to prevent data transmission corruption during probing
and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
Automotive-grade 42MX24 and 42MX36 devices are
compatible with IEEE Standard 1149.1 (informally known
as Joint Testing Action Group Standard or JTAG), which
defines a set of hardware architecture and mechanisms
for cost-effective, board-level testing. The basic MX
boundary-scan logic circuit is composed of the TAP (test
access port), TAP controller, test data registers and
instruction register
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
PRELOAD and BYPASS) and some optional instructions.
Table 1-3 on page 1-9
JTAG testing, while
test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry
1 -8
40MX and 42MX Automotive FPGA Families
TMS
TCK
TDI
JTAG
JTAG
(Figure
Table 1-4 on page 1-9
describes the ports that control
1-13). This circuit supports all
TAP Controller
Instruction
Register
Control Logic
Boundary Scan Register
describes the
Instruction
Decode
v3.1
The TAP controller is a four-bit state machine. The '1's
and '0's represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles.
Automotive-grade 42MX24 and 42MX36 devices support
three types of test data registers: bypass, device
identification, and boundary scan. The bypass register is
selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices
in a test data path. The 32-bit device identification
register is a shift register with four fields (lowest
significant byte (LSB), ID number, part number and
version). The boundary-scan register observes and
controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Register
Bypass
Output
MUX
TDO