BT848 ETC, BT848 Datasheet - Page 94

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

C
PCI Configuration Space
84
ONTROL
R
EGISTER
D
EFINITIONS
Figure 41. PCI Configuration Space Header
cycles. The configuration space registers are stored in dwords and defined by byte
addresses. Therefore a register one byte in length can have a bit definition other
than [7:0] (for example [31:24]), depending on its location in the configuration
space. For a discussion on configuration cycle addressing, refer to Section 3.6.4.1
of the PCI Local Bus Specification, Revision 2.1.
accessed during normal operation. These registers are normally accessed by the
Power On Self Test (POST) code and by the device driver during initialization
time. Software will however read the status register during normal operation when
a PCI bus error occurs and is detected by Bt848.
SEL) pin is high, and AD[1:0] = 00, otherwise the cycle is ignored. The configu-
ration register addresses are each offset by 4, since AD[1:0] = 00.
or read-only registers/bits complete normally with the data discarded. Read ac-
cesses to reserved or unimplemented registers/bits return a data value equal to ze-
ro.
The Bt848 is a single-function device, and only supports type 0 configuration
The configuration space is accessible at all times even though it is not typically
The Configuration Space is accessed when the Initialization Device Select (ID-
Bt848 supports burst R/W cycles. Write operations to reserved, unimplemented,
31
Reserved
Max_Lat
Class Code
Device ID
Status
L848A_A
Header Type 0
Min_Gnt
Base Address 0 Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16 15
Latency Timer
Interrupt Pin
Vendor ID
Command
Single-Chip Video Capture for PCI
Interrupt Line
Revision ID
Reserved
Bt848/848A/849A
Brooktree
0
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
®