BT848 ETC, BT848 Datasheet - Page 66

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

F
DMA Controller
56
UNCTIONAL
Executing Instructions
D
FIFO Over-run
ESCRIPTION
Conditions
Once the DMA controller has achieved synchronization between the FIFO and the
RISC program, it proceeds with executing the RISC instructions. The data in the
FIFO will be aligned with the data bytes expected by the RISC instructions. The
DMA controller reads RISC instructions and performs burst writes from the FIFO.
in the FIFO before executing a WRITE instruction. Setting this FIFO trigger point
optimizes the bus efficiency, by not allowing the DMA controller to access the bus
every time a DWORD enters the FIFO. However, the FIFO trigger point is ignored
in the case where the DMA controller is near the end of an instruction and the num-
ber of DWORDs left to transfer is less than the number of DWORDS in the FIFO.
By allowing the instruction to complete, even if the FIFO is below its trigger point,
the RISC instructions can be flushed sooner for every scan line. Otherwise, the
DMA controller may have to wait for many scan lines before the required number
of DWORDs are present in the FIFO, especially when capturing highly scaled
down images. There may be several horizontal lines before another DWORD en-
ters the FIFO.
structions. In the planar mode, the trigger points for the FIFOs should be set to the
same level, even though the luma data is being stored in the Y FIFO at least twice
as fast the chroma data is being stored in the Cr and Cb FIFOs. This ensures that
the Y FIFO will be selected first to burst data onto the PCI bus.
it is essential to regain control of the bus as soon as possible and to deliver any
queued DWORDs. The DMA controller will ignore the FIFO trigger point as it
needs to empty the FIFO immediately, otherwise it may not have a chance to empty
the rest of the FIFOs before it has to relinquish the bus. This is not a concern in the
packed mode because all three FIFOs are treated as one large FIFO.
reads when the PCI target detects a parity error while the PCI initiator is reading
the instruction data. This condition also causes an interrupt.
There will be cases where the Bt848 PCI initiator cannot gain control of the PCI
bus, and the DMA controller is not able to execute the necessary WRITE instruc-
tions. Instead of writing data to the bus, the DMA controller reads data out of the
FIFO and discards the data. To the FIFO, it appears as if the DMA controller is out-
putting to the bus. This allows the FIFO over-runs to be handled gracefully, with
minimal loss of data. The Bt848 is not required to abort a whole scan during FIFO
over-runs. The DMA controller keeps track of the data to the nearest byte, and is
able to deliver the rest of the scan line in the case the FIFO over-run condition is
cleared.
(FFULL) to determine how full the FIFOs are. However, before the DMA control-
ler begins a burst write operation to process a WRITE instruction, it is desirable to
The DMA controller can be programmed to wait for 4, 8, 16, or 32 DWORDs
The FIFO trigger point is ignored by the DMA controller during all SKIP in-
When the initiator is disconnected from the PCI bus while in the planar mode,
The DMA controller immediately stops burst data writes and RISC instruction
The Bt848 DMA controller is normally monitoring the FIFO Full counters
L848A_A
Single-Chip Video Capture for PCI
Bt848/848A/849A
Brooktree
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