BT848 ETC, BT848 Datasheet - Page 46

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

F
VBI Data Output Interface
Figure 20. VBI Section Block Diagram
36
UNCTIONAL
Analog
Video
D
ESCRIPTION
ADC
Data
VBI
Video Data Format Converter
YCrCb 4:2:2, 4:1:1
CSC/Gamma
8-Bit Dither
abled for the even field and CAPTURE_ODD register bit is enabled for the odd
field. The VBI data is sampled at a rate of 8*Fsc and is stored in the FIFO as a se-
quence of 8-bit samples. Line mode VBI data is horizontally bound beginning at
VBI_HDELAY pixels from the trailing edge of HRESET and ending after the
VBI_PKT number of DWORDs. Line mode VBI data is vertically bound starting
at the first line following VRESET and ending at VACTIVE. VBI register settings
can only be changed on a per frame basis. The VBI timing is illustrated in
Figure 19.
Figure 19. VBI Timing
as any other type of data. It is output over the PCI bus via RISC instructions. If the
number of VBI lines desired by the user is smaller than the entire vertical blanking
region, the extra data will be discarded by the use of the SKIP RISC instruction.
Alternatively, if the user desires a larger VBI region in the VBI line output mode,
the vertical blanking region can be extended by setting the VDELAY register bit to
the appropriate value. The VBI line output mode can in effect extend the VBI re-
gion to the entire field. Figure 20 shows a block diagram of the VBI section.
VBI line data capture occurs when the CAPTURE_EVEN register bit is en-
Once the VBI data has been captured and stored in the Bt848 FIFO, it is treated
VRESET
VACTIVE
VDELAY
Format
MUX
HRESET
L848A_A
# DWORDS
Cb: 35x36
Cr: 35x36
VBI_HDELAY
Y: 70x36
FIFOs
DMA Controller
Address Generator
VBI Line Data Capture
FIFO Data MUX
Single-Chip Video Capture for PCI
Instruction
VBI_PKT #
Queue
PCI Initiator
Bt848/848A/849A
Brooktree
PCI
Bus
®