BT848 ETC, BT848 Datasheet - Page 82

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

E
General Purpose I/O Port
Figure 33. Basic Timing Relationships for SPI Mode
72
LECTRICAL
Digital Video in Support
C
C
DVALID
ACTIVE
GPCLK
R
Y[7:0]
B
C
FLAG
B
(Bt848A/849A Only)
[7:0]
I
NTERFACES
This section describes how to use the Bt848A/849A with a digital camera. The
GPIO port can be configured to accept general digital data streams.
ital video input events from the internal decoder timing. It allows the digital video
input H & V events to synchronize the sequencer and the programmable output
events to be positioned where needed to synchronize the decoder.
eration of timing events. The SRAM is programmed once for interfacing to a given
digital video input standard. The address for the SRAM is a 20-bit shift register
with reset and advance inputs. The SRAM is written in sequence, in byte-mode, af-
ter a reset. Then the SRAM will function normally in video mode. The addr s/r will
be advanced every time the H or V value compares exactly to the HC or VC
counters, or reset when the HRST signal output is active and the HC reaches the fi-
nal H value. These register settings can be found in the Control Register Digital
Video In Support (Bt848A/849A only).
facing to video standards. Software for programming the Bt848A/Bt849A is in-
cluded in the development kit for interfacing to the following standards. Table 14
provides the alternate pin definitions when using the digital video-in mode.
The Bt848A/849A contains an SRAM based state machine that isolates the dig-
A 20 x 20 SRAM is used to store H & V count values and signal values for gen-
The digital input port on the Bt848A and Bt849A provides flexibility for inter-
L848A_A
Single-Chip Video Capture for PCI
Bt848/848A/849A
Brooktree
®