BT848 ETC, BT848 Datasheet - Page 125

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
GPIO and DMA Control
Memory Mapped Location 0x10C – (GPIO_DMA_CTL)
Brooktree
Bits
[12:11]
[9:8]
[7:6]
[5:4]
[3:2]
[15]
[14]
[13]
[10]
[1]
[0]
Type
®
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
00
0
00
00
00
00
0
0
Name
GPINTC
GPINTI
GPWEC
GPIOMODE
GPCLKMODE
Reserved
PLTP23
PLTP1
PKTP
RISC_ENABLE
FIFO_ENABLE
L848A_A
Description
A value of 0 selects the direct non-inv/inv input from GPINTR to go
to the interrupt status register. A value of 1 selects the rising edge
detect of the GPINTI programmed input.
A value of 1 inverts the input from the GPINTR pin immediately
after the input buffer.
A value of 0 enables GPIO inputs to be registered upon the rising
edge of GPWE. A value of 1 enables GPIO inputs to be registered
upon the falling edge of GPWE.
A value of 1 enables CLKx1 to be output on GPCLK. A value of 0
disables the output and enables GPCLK to supply the internal pixel
clock during SPI-16 input mode, otherwise this pin is assumed to
be inactive.
This bit should only be written with a logical zero.
Planar mode trigger point for FIFO2 and FIFO3.
Planar mode trigger point for FIFO1.
Packed mode FIFO Trigger Point. The number of DWORDs in the
FIFOs in total before the DMA controller begins to burst data onto
the PCI bus.
A value of 1 enables the DMA controller to process pixel dataflow
instructions beginning at the RISC program start address.
A value of 1 enables the data FIFO, while 0 flushes or resets it.
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
= Normal GPIO port. See the GPIO section for overriding
= Synchronous Pixel Interface output mode.
= Synchronous Pixel Interface input mode.
= Reserved.
= 4 DWORDs
= 8 DWORDs
= 16 DWORDs
= 32 DWORDs
= 4 DWORDs
= 8 DWORDs
= 16 DWORDs
= 32 DWORDs
= 4 DWORDs
= 8 DWORDs
= 16 DWORDs
= 32 DWORDs
conditions.
C
ONTROL
R
GPIO and DMA Control
EGISTER
D
EFINITIONS
115