ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 98

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
PROTECTING THE FLASH
Two forms of protection are offered for this flash memory: read
protection and write/erase protection. The read protection
ensures that any pages that are read protected are not able to be
read by the end user. The write protection ensures that the flash
memory cannot be erased or written over. This protects the end
system from tampering and can prevent the code from being
overwritten in the event of a unexpected disruption of the
normal execution of the program.
Write/erase protection is individually selectable for all of the
32 pages. Read protection is selected in groups of 4 pages (see
Figure 79 for the groupings). The protection bits are stored in
the last flash memory locations, Address 0x3FFA through
Address 0x3FFF (see Figure 81); 4 bytes are reserved for
write/erase protection, 1 byte is for read protection, and another
byte sets the protection security key. The user must enable read
and write/erase protection for the last page for the entire
protection scheme to work.
Note that the read protection does not prevent MOVC
commands to be executed within the code.
There is an additional layer of protection offered by a protection
security key. The user can set up this security key so that the
protection scheme cannot be changed without this key. Once
the protection key has been configured, it cannot be modified.
Enabling Flash Protection by Code
The protection bytes in the flash memory can be programmed
using flash controller command and programming ECON to 0x08.
In this case, the EADRH, EADRL, PROTB1, and PROTB0 bytes
are used to store the data to be written to the 32 bits of write
protection. Note that the EADRH and EADRL registers are not
used as data pointers here, but to store write protection data.
PROTB1
PROTB0
PROTKY
EADRH
EADRL
PROTR
0x3FFE
0x3FFD
0x3FFC
0x3FFB
0x3FFF
0x3FFA
0x3FF9
0x3E00
Figure 81. Flash Protection in Page 31
WDOG
LOCK
31–28
WP
WP
WP
WP
RP
31
23
15
7
27–24
WP
WP
WP
WP
RP
30
22
14
6
23–20
WP
WP
WP
WP
RP
29
21
13
5
PROTECTION KEY
19–16
WP
WP
WP
WP
RP
28
20
12
4
15–12
WP
WP
WP
WP
RP
27
19
11
3
11–8
WP
WP
WP
WP
RP
26
18
10
2
WP
WP
WP
WP
7–4
RP
25
17
9
1
WP
WP
WP
WP
3–0
RP
24
16
8
0
Rev. PrA | Page 98 of 136
The sequence for writing the protection bits is as follows:
1.
2.
3.
4.
5.
To enable read and write/erase protection for the last page only,
use the following 8051 code. Writing the flash protection
command to the ECON register initiates programming the
protection bits in the flash.
; enable write/erase protection on the last page only
MOV EADRH, #07FH
MOV EADRL, #0FFH
MOV PROTB1, #FFH
MOV PROTB0, #FFH
; enable read protection on the last four pages only
MOV PROTR, #07FH
; set up a protection key of 0A3H. This command can be
; omitted to use the default protection key of 0xFF
MOV PROTKY, #0A3H
; write the flash key to the FLSHKY register to enable flash
; access. The flash access key is not configurable.
MOV FLSHKY, #3BH
; write flash protection command to the ECON register
MOV ECON, #08H
Set up the EADRH, EADRL, PROTB1, and PROTB0
registers with the write/erase protection bits. When erased,
the protection bits default to 1 (like any other bit of flash
memory). The default protection setting is for no
protection. To enable protection, write a 0 to the bits
corresponding to the pages that should be protected.
Set up the PROTR register with the read protection bits.
Note that every read protection bit protects four pages. To
enable the read protection bit, write a 0 to the bits that
should be read protected.
To enable the protection key, write to the PROTKY
register. If enabled, the protection key is required to modify
the protection scheme. The protection key, Flash Memory
Address 0x3FFA, defaults to 0xFF; if the PROTKY register
is not written to, it remains 0xFF. If the protection key is
written to, the PROTKY register must be written with this
value every time the protection functionality is accessed.
Note that once the protection key is configured, it cannot
be modified. Also note that the most significant bit of
Address 0x3FFA is used to enable a lock mechanism for the
watchdog settings (see the Watchdog Timer section for
more information).
Run the protection command by writing 0x0 to the ECON
register.
Reset the chip to activate the new protection.
Preliminary Technical Data