ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 25
ADE7566ASTZF8-RL2
Manufacturer Part Number
ADE7566ASTZF8-RL2
Description
Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
Manufacturer
AD [Analog Devices]
Datasheet
1.ADE7566ASTZF8-RL2.pdf
(136 pages)
- Current page: 25 of 136
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Preliminary Technical Data
Table 19. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit No.
7 to 0
Table 20. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit No.
7 to 0
Table 21. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit No.
7 to 0
Table 22. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit No.
7 to 0
Table 23. Power Control SFR (POWCON, 0xC5)
Bit No.
7
6
5
4
3
2 to 0
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves a double instruction sequence. Global interrupts must first be disabled to ensure that the two
instructions occur consecutively. The Key SFR (KYREG, 0xC1) is set to 0xA7 and is immediately followed by a write to the POWCON SFR.
For example:
CLR EA
MOV KYREG,#0A7h
MOV POWCON, #10H
NOP
NOP
Mnemonic
SCRATCH1
Mnemonic
SCRATCH2
Mnemonic
SCRATCH3
Mnemonic
SCRATCH4
Mnemonic
RESERVED
METER_OFF
RESERVED
COREOFF
RESERVED
CD[2:0]
Default
0
Default
0
Default
0
Default
0
Default
0
0
0
0
0
010
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
Description
Value can be written/read in this register. This value is maintained in all the power-saving modes.
;Disable Interrupts while configuring to WDT
;Write KYREG to 0xA7 to get write access to the POWCON SFR
;Shutdown the core
Description
Reserved.
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
Reserved.
Set this bit to shut down the core if in the PSM1 operating mode.
Reserved.
Controls the core clock frequency, f
CD[2:0]
000
001
010
011
100
101
110
111
Rev. PrA | Page 25 of 136
Result (f
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
CORE
in MHz)
CORE
. f
CORE
= 4.096 MHz/2
CD
.
ADE7566/ADE7569
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