ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 109

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 121. Alarm Interval SFR (INTVAL, 0xA6)
Bit No.
7 to 0
Table 122. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit No.
7 to 0
Table 123. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit No.
7 to 0
Table 124. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit No.
7
6 to 5
4
3 to 1
0
Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)
To protect the RTC from runaway code, a key must be written to the KYREG register to obtain write access to the Interrupt Pins
Configuration SFR (INTPR, 0xFF). The KYREG should be set to 0xEA to unlock this SFR and resets to zero after a timekeeping register is
written to. The RTC registers can be written using the following 8052 assembly code:
MOV
MOV
Table 125. Key SFR (KYREG, 0xC1)
Bit No.
7 to 0
KYREG, #0EAh
INTPR, #080h
Mnemonic
INTVAL
Mnemonic
RTCCAL
FSEL[1:0]
Reserved
INT1PRG[2:0]
INT0PRG
Mnemonic
KYREG
Mnemonic
Mnemonic
RTCCOMP
TEMPCAL
Default
0
Default
0
Default
0
Default
0
Default
0
000
0
The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration
SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a
pending RTC interrupt is created. Note that the interval counter is 8-bits. Therefore, it could count up to
255 sec, for example.
Write 0xA7 to the this SFR before writing to the POWCON SFR, which unlocks KYREG.
Write 0xEA to the this SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping registers to
unlock KYREG.
Description
Description
Description
The RTCCOMP SFR holds the nominal RTC compensation value at 25°C. This register is retained during a
watchdog reset or an external reset. It is reset after a POR.
Description
The TEMPCAL SFR is adjusted based on the temperature read in the TEMPADC to calibrate the RTC over
temperature. This allows the external crystal shift to be compensated over temperature. This register is
retained during a watchdog reset or an external reset. It is reset after a POR.
Description
Controls the RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
Sets RTC calibration output frequency and calibration window.
FSEL[1:0]
0
0
1
1
Controls the function of INT1.
INT1PRG[2:0]
x
x
0
1
Controls the function of INT0.
INT0PRG
0
1
0
0
1
1
0
1
0
1
0
1
x
x
Rev. PrA | Page 109 of 136
Result (Calibration window, frequency)
30.5 sec, 1 Hz
30.5 sec, 512 Hz
0.244 sec, 500 Hz
0.244 sec, 16.384 kHz
Result
GPIO
BCTRL
INT1 input disabled
INT1 input enabled
Result
INT0 input disabled
INT0 input enabled
ADE7566/ADE7569