HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 43

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DESCRIPTOR TABLE, Cont.
3
2
1-0
TRANSMIT MODE CONTROL WORD
Transmit Mode Control Words apply when the command word T/ bit equals one (transmit) and the subaddress field has a
value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior, and conveys
activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be written by the host;
these bits are updated by the device during terminal execution, that is, when Configuration Register 1 STEX bit equals 1. The
host can write bit 2 only when STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by
MR
Control Word address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Processing),
the transmit mode Control Word looks like this:
When SMCP applies, the number of active mode Control Word bits is reduced:
Bit No.
15
14
MSB
MSB
master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any host read cycle to the
15 14 13 12 11 10 9
15 14 13 12 11 10 9
H
H
H
H
STOPP
PPEN
——
Mnemonic Function
IXEQZ
IWA
H
H
H
H
D1 D
D1 X
SMCP Disabled
SMCP Enabled
Stop Ping-Pong Request.
The host asserts this bit to suspend ping-pong buffering for this mode code. The host resets this bit to
ask the
disable status by writing PPON bit 3.
Ping-Pong Buffer Enable.
The PPEN bit is initialized by the host to select buffer mode. If this bit is high, ping-pong buffering is
selected. If this bit is low, indexed single buffering is selected.
After reset, the host initializes this bit to logic 1 to enable ping-pong buffering for this mode code. The
host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the STOPP bit
asks the device to re-enable ping-pong. The device confirms ping-pong enable or disable state
changes by writing the PPON bit.
Not used.
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an
interrupt for mode code commands using indexed buffer mode when the INDX value decrements
from 1 to 0. Upon completion of command processing that results in INDX = 0, when IXEQZ interrupts
are enabled, an IXEQZ interrupt is entered in the Pending Interrupt Register, the
is asserted, and the interrupt is registered in the Interrupt Log.
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation at
each instance of a valid mode code command. Upon completion of command processing, when IWA
D
D
D
X
8
8
X
X
7
7
device
X
X
6
6
X
X
5
5
to re-enable ping-pong. The device confirms recognition of ping-pong enable or
X
X
4
4
HOLT INTEGRATED CIRCUITS
H
X
3
3
X
H
2
2
HI-6120, HI-6121
X
X
1
1
X
X
0
0
LSB
LSB
43
R
D1
D1
H
D
X
H
D
X
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may read logic 0 or 1
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may read logic 0 or 1
INTMES
output pin