HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 101

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

RT MESSAGE RESPONSES, OPTIONS & EXCEPTIONS, Cont.
Circumstances for
Received Message
MC20 EXCEPTIONS
——— AND ———
UMCINV bit in Config.
Register 1 equals 0.
The Illegalization Table
bit equals 1 **
Mode code command
word not followed by a
contiguous data word
(missing data word)
Mode code command
word followed by data
word with Manchester
encoding or parity error
(bad data word)
** Command is illegal and terminal is using “illegal command detection”
Mode code command
with mode code 10101
and T/ bit equals 0
TRANSMITTER
BCR status bit.
T/ bit equals 1
SHUTDOWN
SELECTED
OVERRIDE
R
Continued:
(MC21)
R
Terminal Response
to Received Command
Set Message Error (ME)
status. If not broadcast,
transmit Status Word.
If broadcast, also set
Status Word BCR bit and
suppress Status response.
No Status Word transmit.
Set the Message Error
(ME) status bit.
If broadcast, set the
No Status Word transmit.
Set the Message Error
(ME) status bit.
If broadcast, set the
BCR status bit.
Default response: Reset
Message Error (ME)
status. and transmit
Status Word. If broadcast,
set the BCR status bit and
suppress Status response.
After Status Word transmission, the device stores received data word in the assigned index or
ping-pong buffer (or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies).
If the MCOPT4 bit in Configuration Register 2 equals 0, the received data word is compared
to the value in the Bus Select Register corresponding to the inactive bus. For example, if the
command is received on Bus A, the comparison uses the Bus B Select Register value. If the
compared values match, the device automatically re-enables
inactive bus, regardless of the state of the SDSEL bit in Configuration Register 2. The device
affirms fully reenabled bus status by resetting all four TXASD, TXBSD, RXASD and/or RXBSD
bits in the Built-In Test Register at register address 0x0014. Note: If the TXINHA or TXINHB
input pins are asserted, the device cannot override the resulting hardware transmit inhibit for
the affected bus. In this case, the corresponding TXASD and/or TXBSD bits remain high.
See Built-In Test Register description for further information.
If MCOPT4 bit in Configuration Register 2 equals 1, the IWA interrupt is typically used to alert
the host when an MC21 command is received.
mode data word matches the bus selection criteria. If bus selection criteria is met,
fulfills the “override shutdown” command using one of two options:
(1) reset the bus shutdown bit INHBUSA or INHBUSB for the inactive bus in Configuration
(2) reset the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to reenable
Register 1 to reenable both transmit and receive, if the host used this bit to shut down
transmit and receive for an earlier MC4 or MC20 command. (Resetting this shutdown bit
does not restore bus transmit capability if a TXINHA or TXINHB input pin is asserted.)
transmit if the host used this pin to shut down transmit only for an earlier MC4 or MC20 command.
FOR THE HI-6120 / HI-6121 REMOTE TERMINAL
SUMMARY OF MESSAGE RESPONSES
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
101
or
Bits Updated
in Descriptor
Control Word
DBAC bit set.
BCAST bit updated.
DPB bit toggles.
DBAC bit set.
BCAST bit updated.
DPB bit toggles.
DBAC bit set.
BCAST bit updated.
DPB bit toggles.
DBAC bit reset.
BCAST bit reset.
DPB bit toggles.
The host
must evaluate whether the received
transmit and receive
Bits Updated
in Data Buffer
Msg Info Word
ILCMD bit set.
MERR bit set.
BUSID bit updated.
RTRT bit reset.
(Other error bits reset.)
MERR bit set.
WCTERR bit updated.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
(Other error bits reset.)
MERR bit set.
IWDERR bit set.
BUSID bit updated.
ILCMD bit reset.
RTRT bit reset.
(Other error bits reset.)
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit reset.
(All error bits reset.)
the host
for the
Interrupt
Options
ILCMD
MERR
MERR
IWA
IWA
IWA
IWA
IBR
IBR
IBR