HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 37

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DESCRIPTOR TABLE, Cont.
RECEIVE SUBADDDRESS CONTROL WORD
Receive Subaddress Control Words apply when a valid command word T/ bit equals zero (receive) and the subaddress field
has a value in the range of 1 to 30 (0x1E).
behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot
be written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register 1
STEX bit equals 1. The host can write bits 0-2 and 4-7 only when STEX equals zero; bits 3 and 12-15 can be written anytime.
This register is cleared to 0x0000 by
Following any host read cycle to the Control Word address, the DBAC bit is reset.
Bit No.
15
14
13
MSB
Command
0 0 0 0 0 0 1
Sync
15 14 13 12 11 10 9
0x0
H
for Subaddress Commands
SA4:0 equals 00001 to 11110
H
Descriptor Table Address
Mnemonic Function
IXEQZ
IWA
IBRD
H
RT Addr
TA4:0
H
0x2
D1 D
0
T/
Bit
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high,
interrupt for (a) subaddresses using indexed buffer mode when the INDX value decrements from 1 to
0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages
has been transacted. If enabled, u
an IXEQZ interrupt is entered in the Pending Interrupt Register, output pin
the interrupt is registered in the Interrupt Log.
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation when
the subaddress receives any valid receive command. If enabled, upon completion of command
processing, an IWA interrupt is entered in the Pending Interrupt Register, output pin
asserted, and the interrupt is registered in the Interrupt Log.
Interrupt Broadcast Received.
If the Interrupt Enable Register IBRD bit is high, a
when the subaddress receives a valid broadcast command.
processing an IBRD
asserted
bit is high in Configuration Register 1. In this case, commands to RT address 31 are not recognized
as valid by the device.
R
D
Subaddress
D
8
This figure assumes descriptor table base address = 0x0200.
SA4:0
H
7
, and the interrupt is registered in the Interrupt Log.
H
6
MR
Control Word Address From Command Word
H
5
FIGURE 10. Deriving a Descriptor Table
0 0
master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits.
Word Count
H
4
The descriptor Control Word defines terminal command response and interrupt
HOLT INTEGRATED CIRCUITS
WC4:0
H
3
interrupt is entered in the Pending Interrupt Register, output pin
Command Word’s Subaddress
H
Descriptor Address Format
2
HI-6120, HI-6121
H
1
P
H
0
Depends On
pon completion of
LSB
37
Command
Sync
R
D1
H
D
ssertion of this bit enables interrupt generation
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
assertion of this bit enables generation of an
command processing that results in index = 0,
RT Addr
TA4:0
0 0 0 0 0 0 1
If enabled, upon completion of message
0x0
This bit has no function if the BCSTINV
SA4:0 equals 00000 or 11111
for Mode Code Commands
T/
Descriptor Table Address
Bit
R
Subaddress
0x3
SA4:0
INTMES
1
Mode Code
is asserted, and
MC4:0
INTMES
INTMES
P
0 0
is
is