HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 20

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
INTERRUPT ENABLE REGISTER
This 16-bit register is Read-Write (except bits 2-0 are read only) and is fully maintained by the host. All bits are active high.
After rising edge on the
SRST software reset.
Address registers, and refer to the later section entitled “Interrupt Management”.
An interrupt type is globally disabled when the corresponding bit in this register is reset. This allows the external host or
subsystem to temporarily disable interrupt servicing for some or all interrupts. While an interrupt enable bit is negated, the
terminal does not generate an interrupt output signal for the corresponding interrupt event. Note: Asserting an interrupt bit in
this register after an event occurs does not generate an interrupt for that event. For some interrupts that result from message
processing, interrupt enable bits in a each command’s descriptor Control Word
to respond appropriately to interrupt-causing events:
Bit No.
15
14
13
12-11
10
9
8
MSB
MSB
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
IXEQZ
IWA
IBR
——
MERR
——
ILCMD
Mnemonic Interrupt Type
X
X
MEMORY ADDRESS 15:0
For further information on interrupts, see descriptions for the Pending Interrupt and Interrupt Log
MR
Index Equal Zero Interrupt.
Interrupt When Accessed Interrupt.
Broadcast Command Received Interrupt.
Not used.
Message Error Interrupt.
When this bit is high, the
Not used.
Illegal Command Interrupt.
When this bit is asserted, interrupts are globally enabled for (a) subaddresses using indexed buffer
mode when the index decrements from 1 to 0, and (b) subaddresses using a circular buffer mode
when the pre-determined number of messages has been transacted. When this bit is asserted,
occurrence of an IXEQZ event (a) or (b) causes
command’s descriptor Control Word).
When this bit is asserted, interrupts are globally enabled for each message occurrence to
subaddresses in which the Descriptor Control Word allows the IWA interrupt. When this bit is
asserted, occurrence of an IWA event causes
command’s descriptor Control Word).
When this bit is asserted, interrupts are globally enabled for each broadcast message to
subaddresses in which the Descriptor Control Word allows the IBR interrupt. When this bit is
asserted, occurrence of an IBR event causes
command’s descriptor Control Word).
Errors are caused by Manchester encoding problems or protocol errors. Interrupt assertion occurs
whenever the terminal sets the ME “message error” bit in the terminal’s status word. The detected
error type can be found in
Illegal commands are defined in the Illegalization Table. When enabled, the ILCMD interrupt is
asserted when the Illegalization Table bit corresponding to the received command is logic 1. The
Illegalization Table should only contain nonzero values when “illegal command detection” is being
X
Master Reset input, the register is automatically initialized to 0x0007. This register is unaffected by
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
(0x0010)
HOLT INTEGRATED CIRCUITS
3
3
3
1
2
2
2
Message Information Word stored as a result of message processing.
HI-6120, HI-6121
INTMES
1
1
1
1
1
0
0
0
LSB
LSB
interrupt output is asserted when a message error is detected.
20
INTMES
INTMES
INTMES
act in combination with settings in this register
output assertion (if the IXEQZ bit is set in the
output assertion (if the IWA bit is set in the
output assertion (if the IBR bit is set in the