FL103 FAIRCHILD [Fairchild Semiconductor], FL103 Datasheet - Page 11

• Manufacturer Part Number: FL103
• Description: Primary-Side-Regulation PWM Controller for LED Illumination
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
voltage at the end of the diode conduction time (t
the output voltage (V
internal error amplifier for output voltage regulation
(EAV) compares the sampled voltage with an internal
precise reference to generate error voltage (V
which determines the duty cycle of the MOSFET (Q1) in
Constant Voltage Mode.
Constant Current Regulation
The output current (I
drain current (I
(t
the diode current (I
current estimator (I
value of the drain current with a peak detection circuit
and calculates the output current (I
discharge time (t
output information is compared with an internal precise
reference to generate error voltage (V
determines the duty cycle of the MOSFET (Q1) in
Constant Current Mode. With Fairchild’s innovative
technique TRUECURRENT™, constant current output
can be precisely controlled.
Voltage and Current Error Amplifier
Of the two error voltages, V
one determines the duty cycle. Therefore, during
Constant Voltage Regulation Mode, V
the duty cycle while V
Constant Current Regulation Mode, V
the duty cycle while V
Operating Current
The operating current is typically 3.2mA. The small
operating current results in higher efficiency and
reduces the V
FL103 enters Green Mode, the operating current is
reduced to 0.95mA, assisting the power supply in
meeting power conservation requirements.
Green Mode Operation
The FL103 uses voltage regulation error amplifier output
(V
the PWM frequency, as shown in Figure 22. The
switching frequency decreases as load decreases. In
heavy load conditions, the switching frequency is fixed
at 50kHz. Once V
frequency linearly decreases from 50kHz. When FL103
enters into green load, the PWM frequency is reduced
to a minimum frequency of 370Hz., gaining power
saving power
conservation requirements.
DIS
Figure 22.
COMV
) since output current (I
) as an indicator of the output load and modulates
Switching Frequency as Output Load
DD
PK
to help meet international power
) and inductor current discharge time
COMV
DIS
capacitor (C
O
F_AVG
O
O
) and switching period (t
COMV
) information can be obtained. The
) can be estimated using the peak
COMI
Estimator) determines the peak
decreases below 2.5V, the PWM
) in steady state. The output
is saturated to HIGH.
is saturated to HIGH. During
O
) is same as the average of
COMV
VDD
) requirement. Once
and V
O
) using the inductor
COMV
COMI
COMI
COMI
, the small
determines
determines
), which
S
). This
COMV
DIS
),
),
11
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. FL103 has an internal frequency hopping
circuit that changes the switching frequency between
47kHz and 53kHz.
High-Voltage Startup
Figure 23 shows the startup block. The HV pin is
connected to the line input or DC link capacitor (C
During startup, the internal startup circuit is enabled.
Meanwhile, line input supplies the current (I
charge the V
reaches V
brownout, the internal startup circuit is disabled,
blocking I
turns on, C
consumption current before the PWM starts to switch.
Thus, C
(7.5V) before the power can be delivered from the
auxiliary winding. To avoid the surge from input source,
the R
recommended value of 100kΩ.
Protections
The FL103 has several self-protection functions; over-
voltage
brownout protection, and pulse-by-pulse current limit.
V
The turn-on and turn-off thresholds are fixed internally at
16V and 7.5V, respectively. During startup, the V
capacitor (C
capacitor (C
be delivered from the auxiliary winding of the main
transformer. V
during this startup process. This UVLO hysteresis
window ensures that V
supplies V
V
The
conditions. If the V
feedback condition, the OVP is triggered and the PWM
switching is disabled. The OVP has a debounce time
(typically 200µs) to prevent false triggering due to
switching noises.
Thermal Shutdown Protection (TSD)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
There is a hysteresis of 15°C.
DD
DD
Under-Voltage Lockout (UVLO)
Over-Voltage Protection (OVP)
Start
OVP
VDD
Start
protection,
DD
DD-ON
is connected between C
VDD
VDD
must be large enough to prevent V
VDD
DD
during startup.
from flowing into the HV pin. Once the IC
Figure 23.
prevents
is the only energy source to supply the IC
DD
) continues to supply V
) must be charged to 16V. The V
capacitor (C
(16V) and V
is not allowed to drop below 7.5V
DD
voltage exceeds 28V at open-loop
thermal
DD
damage
Startup Block
VDD
DC
capacitor (C
). When the V
is enough high to avoid
shutdown
DC
from
DD
and HV, with a
until power can
VDD
over-voltage
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protection,
) properly
DD
Start
voltage
DD-OFF
) to
DC
DD
DD
).