K4T1G084QD SAMSUNG [Samsung semiconductor], K4T1G084QD Datasheet - Page 22

• Manufacturer Part Number: K4T1G084QD
• Description: 1Gb D-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

4. Differential data strobe
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
K4T1G084QD
K4T1G164QD
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential
mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guar-
anteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be
tied externally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
correlation.
specifications and device operation are guaranteed for the full voltage range specified.
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
RPRE
t
DQS
DQS
WPRE
V
V
t
t
CL
IH
IL
DQSQmax
(ac)
(ac)
<Data output (read) timing>
t
DMin
DS
D
<Data input (write) timing>
t
DQSH
20 of 29
V
t
V
QH
IH
IL
(ac)
Q
(ac)
t
DMin
DS
D
t
DQSL
Q
DMin
D
t
DH
V
V
IH
IL
(dc)
(dc)
t
DQSQmax
Q
DMin
D
t
DH
V
V
IH
IL
t
(dc)
WPST
(dc)
t
t
RPST
QH
Q
Rev. 1.0 March 2007
DDR2 SDRAM