K4T1G084QD SAMSUNG [Samsung semiconductor], K4T1G084QD Datasheet - Page 19

• Manufacturer Part Number: K4T1G084QD
• Description: 1Gb D-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4T1G084QD
K4T1G164QD
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input tIPW
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ sig-
nals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Active to active command period for 2KB page
size products
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read com-
mand
Exit active power down to read command
Exit active power down to read command
(slow exit, lower power)
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
Symbol
tRFC + 10
min(tCL,t
WR+tRP
tAC min
2* tAC
- 0.25
8 - AL
tQHS
2500
tHP -
- 400
- 350
0.45
0.45
0.35
0.35
min
CH)
125
0.35
min
250
175
200
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
50
0.6
10
35
45
7.5
15
2
2
2
2
x
x
x
DDR2-800
tAC max
tAC max
tAC max
8000
max
17 of 29
0.55
0.55
0.25
200
300
400
350
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
WR+tRP
min(tCL,
tAC min
2*tAC
7 - AL
tQHS
3000
tHP -
-0.25
-400
tCH)
0.45
0.45
0.35
0.35
0.35
37.5
min
-450
175
100
0.35
275
200
200
min
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
7.5
15
x
2
2
2
2
x
x
DDR2-667
tAC max
tAC max
tAC max 2* tACmin tAC max 2* tACmin
+400
8000
max
0.55
0.55
0.25
+450
240
340
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
WR+tRP
min(tCL,
tAC min
6 - AL
tQHS
tHP -
-0.25
3750
0.45
0.45
tCH)
0.35
0.35
37.5
min
-500
-450
225
100
0.35
375
250
200
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
10
50
15
2
2
2
x
x
x
2
DDR2-533
tAC max
tAC max
+500
+450
8000
max
0.55
0.55
0.25
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
min(tCL,
WR+tRP
tAC min
6 - AL
tQHS
5000
tHP -
-0.25
Rev. 1.0 March 2007
tCH)
-600
-500
0.45
0.45
0.35
0.35
0.35
37.5
min
275
150
0.35
475
350
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
15
10
x
2
2
2
2
x
x
DDR2 SDRAM
DDR2-400
tAC max
tAC max
tAC max
+600
+500
max
0.55
0.55
8000
0.25
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
Notes
15,16,
15,16,
14,16,
14,16,
20,21
17,20
17,21
18,23
18,22
9, 10
24
27
27
22
21
19
28
28
12
12
23
33
11
9