AM41DL6408H8H70IS AMD [Advanced Micro Devices], AM41DL6408H8H70IS Datasheet - Page 10
AM41DL6408H8H70IS
Manufacturer Part Number
AM41DL6408H8H70IS
Description
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM41DL6408H8H70IS.pdf
(66 pages)
- Current page: 10 of 66
- Download datasheet (2Mb)
PIN DESCRIPTION
A18–A0
A21–A19, A-1 = 4 Address Inputs (Flash)
SA
DQ15–DQ0
CE#f
CE#s
OE#
WE#
RY/BY#
UB#s
LB#s
CIOf
CIOs
RESET#
WP#/ACC
V
V
V
NC
8
CC
CC
SS
f
s
= Output Enable (Common)
= Ready/Busy Output
= Lower Byte Control (SRAM)
= I/O Configuration (Flash)
= I/O Configuration (SRAM)
= 19 Address Inputs (Common)
= Highest Order Address Pin (SRAM)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
= Chip Enable (SRAM)
= Write Enable (Common)
= Upper Byte Control (SRAM)
= Hardware Reset Pin, Active Low
= Hardware Write Protect/
= Flash 3.0 volt-only single power sup-
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
Byte mode
CIOf = V
CIOf = V
CIOs = V
CIOs = V
Acceleration Pin (Flash)
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
IH
IL
IH
IL
= Byte mode (x8)
= Word mode (x16),
= Byte mode (x8)
= Word mode (x16),
A D V A N C E
Am41DL6408H
I N F O R M A T I O N
LOGIC SYMBOL
19
A21–A19, A-1
SA
CE#f
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
CIOf
CIOs
A18–A0
DQ15–DQ0
RY/BY#
November 24, 2003
16 or 8
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