AM41DL6408H8H70IS AMD [Advanced Micro Devices], AM41DL6408H8H70IS Datasheet
AM41DL6408H8H70IS
Related parts for AM41DL6408H8H70IS
AM41DL6408H8H70IS Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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ADVANCE INFORMATION Am41DL6408H Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE ...
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GENERAL DESCRIPTION Am29DL640H Features The Am29DL640H megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . ...
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Figure 32. SRAM Write Cycle—CE1#s Control .............................. 57 Figure 33. SRAM Write Cycle—UB#s and LB#s Control ................ 58 Flash Erase And Programming Performance . . . 59 Latchup Characteristics . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Standard Voltage Range: Options V = 2.7–3 Max Access Time (ns) CE#f Access (ns) OE# Access (ns) MCP BLOCK DIAGRAM A21 to A0 A21 to ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & COMMAND CE# REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux ...
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CONNECTION DIAGRAM LB UB A18 A17 G1 ...
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PIN DESCRIPTION A18– Address Inputs (Common) A21–A19, A Address Inputs (Flash Highest Order Address Pin (SRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am41DL640 AMD DEVICE NUMBER/DESCRIPTION Am41DL6408H Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640H 64 Megabit (8 ...
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Table 1. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash ± ...
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Table 2. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# SA (Notes Read from Flash Write to Flash ...
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Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# SA (Notes Read from Flash Write to Flash ...
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Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash L ...
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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. ...
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the device is deselected during erasure or program- ming, the device draws active current until the operation is completed the table represents the standby current spec- CC3 ification. Automatic ...
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Table 5. Am29DL640H Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA23 0010000xxx SA24 0010001xxx SA25 0010010xxx SA26 0010011xxx SA27 0010100xxx SA28 0010101xxx SA29 0010110xxx SA30 0010111xxx SA31 0011000xxx SA32 0011001xxx SA33 0011010xxx ...
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Table 5. Am29DL640H Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA71 1000000xxx SA72 1000001xxx SA73 1000010xxx SA74 1000011xxx SA75 1000100xxx SA76 1000101xxx SA77 1000110xxx SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx ...
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Table 5. Am29DL640H Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 1110101xxx SA125 1110110xxx SA126 1110111xxx SA127 1111000xxx SA128 1111001xxx SA129 1111010xxx ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected ...
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method described in “Sector/Sector Block Protection and Unprotection”. If the system asserts V on the WP#/ACC pin, the de- IH vice reverts to whether sectors 0, 1, 140, and 141 were last set ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is ...
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START If data = 00h, RESET# = SecSi Sector unprotected. If data = 01h, SecSi Sector is Wait 1 µs protected. Write 60h to any address Remove ...
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Table 10. CFI Query Identification String Addresses Addresses (Word Mode) (Byte Mode) 10h 20h 11h 22h 12h 24h 13h 26h 14h 28h 15h 2Ah 16h 2Ch 17h 2Eh 18h 30h 19h 32h 1Ah ...
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31h 62h 32h 64h 33h 66h 34h 68h 35h 6Ah 36h 6Ch 37h 6Eh 38h 70h 39h 72h 3Ah 74h 3Bh 76h 3Ch 78h November 24, 2003 ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 14 defines the valid register command sequences. Writing incorrect address and data val- ...
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Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 14 for program command sequence. Figure 4. Program ...
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the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, ...
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Table 14. Am29DL640H Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe the function ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied ...
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CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I Reset Leakage Current LR I ACC Input Leakage ...
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CHARACTERISTICS SRAM DC AND OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current Average Operating Current CC1 ...
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CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V ...
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CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 14. Timing Diagram for Alternating Between November 24, 2003 ...
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CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ...
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CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode ...
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CHARACTERISTICS Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High ...
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CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low ...
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CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address, PD ...
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CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes: 1. ...
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CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 22. Back-to-back Read/Write Cycle Timings t ...
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CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last ...
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CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for ...
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CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect ...
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CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold ...
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CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a ...
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CHARACTERISTICS SRAM Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE ...
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CHARACTERISTICS Address CE#1s CE2s OE# Data Out High-Z Notes CIOs is low, ignore UB#s/LB#s timing and t are defined as the time at ...
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CHARACTERISTICS SRAM Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write ...
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CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing measured from CE1#s going low ...
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CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled, CIOs must be high measured from CE1#s going low to the end ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. ...
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SRAM DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t Data Retention Set-Up Time SDR t Recovery Time RDR Notes: 1. CE1#s ≥ ...
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PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm November 24, 2003 Am41DL6408H 61 ...
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REVISION SUMMARY Revision A (September 17, 2003) Initial release. Revision A+1 (November 24, 2003) Corrected DC characteristics for test condition I Vol (Output Low Voltage). See DC Characteristics - CMOS Compatible table. November ...
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Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro ...
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Sales Offices and Representatives North America ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...