9DB1933AKLF IDT [Integrated Device Technology], 9DB1933AKLF Datasheet - Page 7

• Manufacturer Part Number: 9DB1933AKLF
• Description: Nineteen Output Differential Buffer for PCIe Gen3
• Manufacturer: IDT [Integrated Device Technology]

IDT
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2
3
4
5
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7
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9
10
set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the
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is measured at the outputs of two separate 9DB1933 devices driven by a single main clock in Spread Spectrum mode. The 9DB1933's
must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear
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Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = T
Guaranteed by design and characterization, not 100% tested in production. C
Measured from differential cross-point to differential cross-point
VT = 50% of Vout
PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input.
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
This parameter is deterministic for a given device
Measured with scope averaging on to find mean value.
Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
This parameter is an absolute value. It is not a double-sided figure.
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
This parameter is measured at the outputs of two separate 9DB1933 devices driven by a single main clock. The 9DB1933's must be
t is the period of the input clock
Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB1933 devices This parameter
Skew, Output to Output
®
Skew, Input to Output
Duty Cycle Distortion
Jitter, Cycle to cycle
Nineteen Output Differential Buffer for PCIe Gen3
PLL Jitter Peaking
DIF_IN, DIF [x:0]
DIF_IN, DIF [x:0]
COM;
PLL Bandwidth
PARAMETER
Duty Cycle
DIF[X:0]
DIF[X:0]
Supply Voltage VDD = 3.3 V +/-5%
SYMBOL
t
SSTERROR
∆t
∆t
t
t
t
t
jcyc-cyc
JPEAK
t
pdBYP
BW
pdPLL
pd_BYP
pd_PLL
t
t
t
DCD
JPH
sk3
DC
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating
ranges)
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating
ranges)
Differential Phase Jitter (RMS Value)
Differential Spread Spectrum Tracking Error (peak
to peak)
Measured differentially, Bypass Mode @100MHz
Bypass Mode, nominal value @ 25° C, 3.3V,
PLL Mode, nominal value @ 25° C, 3.3V,
Measured differentially, PLL Mode
Additive Jitter in Bypass Mode
-3dB point in Low BW Mode
-3dB point in High BW Mode
Peak Pass band Gain
CONDITIONS
V
V
PLL mode
V
T
T
T
= 50%
= 50%
= 50%
7
LOAD
= 2pF
2500
MIN
100
0.7
45
-2
2
3700
|500|
|250|
TYP
49.5
300
100
1.4
40
40
25
3
1
1
2
MAX
4500
|600|
|350|
500
150
1.4
55
10
80
50
50
4
2
2
1676A—07/12/10
UNITS NOTES
MHz
MHz
dB
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
1,2,4,6,
1,2,3,6,
1,7,10
1,7,12
7,8,9,
7,8,9,
1,2,5
1,2,4
1,2,3
1,2
1,2
1,2
13
13
1
1
1
1