9DB1933AKLF IDT [Integrated Device Technology], 9DB1933AKLF Datasheet - Page 3

• Manufacturer Part Number: 9DB1933AKLF
• Description: Nineteen Output Differential Buffer for PCIe Gen3
• Manufacturer: IDT [Integrated Device Technology]

Pin Description
IDT
PIN #
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
®
1
2
3
4
5
6
7
8
9
Nineteen Output Differential Buffer for PCIe Gen3
IREF
GNDA
VDDA
HIGH_BW#
VDD
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
SMBCLK
SMBDAT
OE5#
DIF_5
DIF_5#
OE6#
DIF_6
DIF_6#
VDD
GND
OE7#
DIF_7
DIF_7#
OE8#
DIF_8
DIF_8#
SMB_A0
SMB_A1
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 =disable outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
3
DESCRIPTION
1676A—07/12/10