AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 8

• Manufacturer Part Number: AM79Q4457J
• Description: Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

PIN DESCRIPTIONS
8
FSR
FSX
FSR
FSX
Pin Name
I
CS
I1
I1
I1
CS
I1
REF1
CCLK
IN1
IN2
IN3
IN4
DRA
DXA
I
A/µ
CO
1
1
1
REF3
3
3
3
CI
, CS
, FSR
, FSX
, I2
, I2
, I2
, I
, CS
, FSR
, FSX
, I2
REF2
IN1
IN2
IN3
IN4
2
4
,
,
,
,
,
2
2
4
4
,
,
Current
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
A-law or µ-law Select. The A-law/µ-law select pin is used to inform the QSLAC-NP device which
compression/expansion standard to use. A logic Low signal (0 V) on the A-law/µ-law pin selects
the µ-law standard, and a logic High (+5 V) selects the A-law standard. The A-law/µ-law input can
be connected to V
device can be programmed for A-law by connecting the A/µ input to V
for µ-law by connecting the device pin to DGND.
(Am79Q4457 Device Only) Control Clock. The Control Clock input shifts data into and out of the
Serial Interface of the QSLAC-NP device. The maximum clock rate is 4.096 MHz. (Serial control
on the Am79Q4457 device only.)
(Am79Q4457 Device Only) Control Data. Control Data is written into the selected Channel Control
Register (see CS
data rate is determined by CCLK. (Serial control on the Am79Q4457 device only.)
(Am79Q4457 Device Only) Control Data. Control Data is read in serial form from the Enabled
Channel Register (see CS
determined by the Control Clock (CCLK). (Serial control available on the Am79Q4457 device only.)
(Am79Q4457 Device Only) Chip Select. The Chip Select (CS
Channel N of the device so that control data can be written to or read from the channel. CS
enables Channel 1, CS
4. (Serial control on the Am79Q4457 device only.)
PCM. The PCM data for Channels 1, 2, 3, and 4 is serially received on the DRA port during the time
slot determined by the Receive Frame Sync Signal (FSR
first. A byte of data for each channel is received every 125 µs at the PCLK rate.
PCM. The transmit data from Channels 1, 2, 3, and 4 is sent serially out the DXA port during
time slots determined by the Transmit Frame Sync (FSX
transmitted with the MSB first. The output is available every 125 µs and the data is shifted out
in 8-bit bursts at the PCLK rate. DXA is high impedance between time slots.
Receive Frame Sync. The Receive Frame Sync pulse for Channel N is an 8 kHz signal that
identifies the receive time slot for Channel N on a system’s receive PCM frame. The QSLAC-
NP device references channel time slots with respect to this input, which must be
synchronized to PCLK. There are both Long-Frame Sync and Short-Frame Sync modes
available on the QSLAC-NP device.
Transmit Frame Sync. The Transmit Frame Sync pulse for Channel N is an 8 kHz signal that
identifies the transmit time slot for Channel N during the system’s transmit PCM frame. The
QSLAC-NP device references individual channel time slots with respect to this input, which
must be synchronized to PCLK. There are both Long Frame Sync and Short Frame Sync
modes available on the QSLAC-NP device.
(I2
to the I
(summing node). I
processed and encoded, and then made available at the TTL-compatible PCM output (DXA).
There are two inputs per channel in the 44-pin QSLAC-NP device. I1
I2
1 and 2 of Channel 3; and I1
details.
(I
internal reference voltage, which is the same as the voltage on the V
I
to-D) converter to encode the signal current present on Iy
input number [1 or 2]) into digital form. By setting different levels for I
transmit gains can be achieved. The reference current used by a channel A-to-D is determined
by the Transmit Gain Select (TGS) bits in the channel control register. The absolute transmit gain
is determined by the reference current selected and the input resistance connected to I
Figure 9 and Table 2 for more details.
REFn
REF2
IN1
IN
on Am79Q4457 Device Only) Analog Inputs. The analog voice band voltage signal is applied
is input 2 of Channel 1; I1
(n = 1, 2, or 3) to ground sets one of three reference currents used by the Analog-to-Digital (A-
and I
IN
input of the QSLAC-NP device through a resistor. The I
REF3
on Am79Q4457 Device Only). Reference Current. The I
Am79Q4457/5457 Data Sheet
N
IN
CCD
) via the CI pin. The data is shifted in the Most Significant Bit (MSB) first. The
is biased at the voltage on the V
directly, eliminating the need for a external pull-up resistor. Therefore, the
2
enables Channel 2, CS
N
) via the CO pin. Data is shifted out with the MSB first. The data rate is
IN4
IN2
and I2
and I2
IN4
IN2
are inputs 1 and 2 of Channel 4. See Figure 9 for more
are inputs 1 and 2 of Channel 2; I1
Description
3
enables Channel 3, and CS
REF1
pin. The audio signal is sampled, digitally
N
N
INn
). Data is always received with the MSB
) signal for that channel. Data is always
(n = channel number [1 to 4] and y =
N
) input (active Low) enables
IN
input is a virtual AC ground input
REF1
IN1
CCD
REF
is input 1 of Channel 1 and
pin. A resistor placed from
REFx
and can be programmed
outputs are biased at the
, three different
IN3
4
and I2
enables Channel
IN3
are inputs
IN
. See
1