AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 24

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AM79Q4457J

Manufacturer Part Number
AM79Q4457J
Description
Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet

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PCM Highway Timing (Long Frame Sync Mode)
OPERATING THE QSLAC-NP DEVICES
The following describes the operation of the four indepen-
dent channels of the QSLAC-NP device. The description
is valid for Channel 1, 2, 3, or 4; consequently, the chan-
nel subscripts have been dropped. For example, VOUT
refers to either VOUT1, VOUT2, VOUT3, or VOUT4.
Also, the additional features provided by the Am79Q4457
device (over the Am79Q5457 device) are described.
Power-Up Sequence
The signal pins have protection diodes to V
ground; consequently, if the signal leads are connected
before V
limited in order to prevent latch-up of the part. Following
initial power application, it is necessary to place all chan-
nels in an inactive state. This ensures a hardware reset is
initiated upon activation of any channel. For these rea-
sons, the following power-up sequence is recommended:
1. V
2. Signal connections
3. In the case of device Am79Q5457, take pins PDN1,
24
FSX/FSR
PCLK
TSCA
PDN2, PDN3, and PDN4 to a logic high state, (de-
vice Am79Q4457 will default to all channels pow-
ered down).
DRA
DXA
CC
and ground
CC
37
or ground, the transient signal current must be
28
1
26
First
First
Bit
26
Bit
36
37
2
25
23
2
2
Am79Q4457/5457 Data Sheet
22
3
CC
32
27
and
3
3
24
21
34
4
Following any subsequent occurrence of all channels
inactivated, upon activation of any channel, a hardware
reset will be initiated.
Master Clock
The master clock, MCLK, is used to derive internal
clocks and timing signals. The master clock must be
essentially jitter free and it must be an integer multiple
of the frame sync frequency. The allowed frequencies
for MCLK are 1.536 MHz, 1.544 MHz, 2.048 MHz, and
4.096 MHz. Internal circuitry determines the MCLK fre-
quency based on the FSX inputs and adjusts the inter-
nal timing circuitry automatically.
4
4
5
35
5
5
8
8
8
30
33
20031A-007
9

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