AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 25

• Manufacturer Part Number: AM79Q4457J
• Description: Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

CONTROL OF THE Am79Q4457/5457
QSLAC-NP DEVICES
The QSLAC-NP device is controlled either directly via
device pins (PDN and A/µ for the Am79Q5457 device) or
through the serial control interface (Am79Q4457 device).
Parallel Control (Am79Q5457 Device)
The Am79Q5457 QSLAC-NP device is controlled di-
rectly via device pins. There are two different control
input pins on the Am79Q5457 device, an A-law/µ-law
select (A/µ) pin and four power-down (PDN) pins, one
per channel. Logic levels on these pins determine the
operating state of the individual channels, active (power-
up) or idle (power-down), and A-law or µ-law operation.
Each channel of the QSLAC-NP device can operate in
either the Powered-Up (Active) or Powered-Down
(Standby) mode. In the Active mode, individual chan-
nels of the QSLAC
ceive PCM and analog information. The Active mode is
required when a telephone call is in progress. The
Standby mode requires the least amount of power per
channel and should be used whenever the line circuit is
on hook and a telephone call is not in progress.
Power Down Input (PDN
0 — Powers the channel up
1 — Powers the channel down
A-Law/µ-Law Select Input (A/µ):
0 — Selects µ-law operation
1 — Selects A-law operation
Note:
PDN is loaded first.
PDN
™
RSVD
device are able to transmit and re-
n
):
RSVD
TGS2
SLAC Products
Serial Control Register
(Am79Q4457 Device Only)
The Am79Q4457 device provides an A-law/µ-law se-
lect pin in the same manner as the Am79Q5457 de-
vice. The Am79Q4457 QSLAC-NP device provides
several additional features over the Am79Q5457 de-
vice. The Am79Q4457 device provides the ability to
program three different gain levels on both the transmit
and receive side of each channel. One of two balance
impedances (connected externally) can be selected on
a per-channel basis with the Am79Q4457 device. The
individual channels of the Am79Q4457 device can be
powered down. Control of the power-down function is
through the per-channel serial control register.
Each channel of the Am79Q4457 QSLAC-NP device
contains a serial shift register and latch in order to eas-
ily control the additional functionality of the device. The
registers are connected as shown in Figure 7. The
channel control registers are enabled for reading or
writing by their corresponding Chip Select (CS
Data on the Control Input (CI) is shifted into the en-
abled register by the Control Clock (CCLK). Each
channel register contains a Balance Network Select
(BNS1) bit, two Receive Gain Select (RGS1/2) bits, two
Transmit Gain Select (TGS1/2) bits and a Power-Down
(PDN) bit. As indicated in Figure 7, the PDN bit is the
most significant bit in the register and is shifted in first.
The balance network select bit is the least significant
bit and is shifted in last.
The Balance Network is selected with the BNS1 bit,
where:
0 —Selects the balance network connected to I1
1 —Selects the balance network connected to I2
Transmit and Receive gains are selected according to
the TGS1/2 and RGS1/2 bits as shown in the gain se-
lect tables, Table 2 and Table 3. The register layout for
each channel is as follows:
RGS2
the channel.
the channel.
TGS1
RGS1
BNS1
n
) signal.
IN
IN
of
of
25